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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9775 * one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 14-bit, 160 msps 2 /4 /8 interpolating dual txdac+ d/a converter functional block diagram differential clk cos sin half- band filter 1 16 image rejection/ dual dac mode bypass mux i and q noninterleaved or interleaved data write select clock out ha lf-band filters also can be configured for "zero stuffing only" * gain dac offset dac f dac /2, 4, 8 sin cos i/q dac gain/offset registers ioffset vref ( f dac ) phase detector and vco prescaler pll clock multiplier and clock divider 16 16 /2 16 data assembler 16 16 16 16 16 16 mux control /2 /2 i latch q latch /2 half- band filter 2 half- band filter 3 *** ad9775 spi interface and control registers filter bypass mux idac idac i out features 14-bit resolution, 160/400 msps input/output data rate selectable 2 /4 /8 interpolating filter programmable channel gain and offset adjustment f s /4, f s /8 digital quadrature modulation capability direct if transmission mode for 70 mhz + ifs enables image rejection architecture fully compatible spi port excellent ac performance sfdr C71 dbc @ 2 mhzC35 mhz wcdma acpr C71 db @ if = 71 mhz internal pll clock multiplier selectable internal clock divider versatile clock input differential/single-ended sine wave or ttl/cmos/lvpecl compatible versatile input data interface twos complement/straight binary data coding dual-port or single-port interleaved input data single 3.3 v supply operation power dissipation: typical 1.2 w @ 3.3 v on-chip 1.2 v reference 80-lead thermally enhanced tqfp package general description the ad9775 is the 14-bit member of the ad977x pin-compatible, high performance, programmable 2 /4 /8 interpolating txdac+ family. the ad977x family features a serial port interface (spi) providing a high level of programmability, thus allowing for enhanced system-level options. these options include: select- able 2 /4 /8 interpolation filters; f s /2, f s /4, or f s /8 digital quadrature modulation with image rejection; a direct if mode; programmable channel gain and offset control; programmable internal clock divider; straight binary or two? complement data interface; and a single-port or dual-port data interface. the selectable 2 /4 /8 interpolation filters simplify the require- ments of the reconstruction filters while simultaneously enhancing the txdac+ family? pass-band noise/distortion performance. the independent channel gain and offset adjust registers allow the user to calibrate lo feedthrough and side band suppression (continued on page 2) applications communications analog quadrature modulation architectures 3g, multicarrier gsm, tdma, cdma systems broadband wireless, point-to-point microwave radios instrumentation/ate txdac+ is a registered trademark of analog devices, inc. * protected bu u.s. patent numbers 5568145, 5689257, and 5703519. other patents pending.
rev. 0 ad9775 C2C (continued from page 1) errors associated with analog quadrature modulators. the 6 db of gain adjustment range can also be used to control the output power level of each dac. the ad9775 features the ability to perform f s /2, f s /4, and f s /8 digi tal modulation and image rejection when combined with an analog quadrature modulator. in this mode, the ad9775 ac- cepts i and q complex data (representing a single or multicarrier wave form), generates a quadrature modulated if signal along with its or thogo nal representation via its dual dacs, and presents these two reconstructed orthogonal if carriers to an analog quadrature modulator to complete the image rejection upconversion pro cess. another digital modulation mode (i.e., the direct if mode) allows the original baseband signal repre- sentation to be fre quency translated such that pairs of images fall at multiples of one-half the dac update rate. the ad977x family includes a flexible clock interface accepting differential or single-ended sine wave or digital logic inputs. an internal pll clock multiplier is included and generates the necessary on-chip high frequency clocks. it can also be disabled to allow the use of a higher performance external clock source. an internal programmable divider simplifies clock generation in the converter when using an external clock source. a flexible data input interface allows for straight binary or two? complement formats and supports single-port interleaved or dual-port data. dual high performance dac outputs provide a differential current output programmable over a 2 ma to 20 ma range. the ad9775 is manufactured on an advanced 0.35 micron cmos process, operates from a single supply of 3.1 v to 3.5 v, and consumes 1.2 w of power. targeted at wide dynamic range, multicarrier and m ultistandard systems, the superb baseband performance of the ad9775 is ideal for wideband cdma, multicarrier cdma, multicarrier tdma, multicarrier gsm, and high performance systems employing high order qam modulation schemes. the image rejection feature simplifies and can help to reduce the number of signal band filters needed in a transmit signal chain. the direct if mode helps to eliminate a costly mixer stage for a variety of communications systems. product highlights 1. the ad9775 is the 14-bit member of the ad977x pin- compatible, high performance, programmable 2 /4 /8 interpolating txdac+ family. 2. direct if transmission capability for 70 mhz + ifs through a novel digital mixing process. 3. f s /2, f s /4, and f s /8 digital quadrature modulation and user- selectable image rejection to simplify/remove cascaded saw filter stages. 4. a 2 /4 /8 user-selectable interpolating filter eases data rate and output signal reconstruction filter requirements. 5. user-selectable two? complement/straight binary data coding. 6. user-programmable channel gain control over 1 db range in 0.01 db increments. 7. user-programmable channel offset control 10% over the fsr. 8. ultra high speed 400 msps dac conversion rate. 9. internal clock divider provides data rate clock for easy interfacing. 10. flexible clock input with single-ended or differential input, cmos, or 1 v p-p lo sine wave input capability. 11. low power: complete cmos dac operates on 1.2 w from a 3.1 v to 3.5 v single supply. the 20 ma full-scale current can be reduced for lower power operation and several sleep functions are provided to reduce power dur- ing idle periods. 12. on-chip voltage reference: the ad9775 includes a 1.20 v temperature compensated band gap voltage reference. 13. 80-lead thermally enhanced tqfp.
rev. 0 C3C ad9775 dc specifications parameter min typ max unit resolution 14 bits dc accuracy 1 integral nonlinearity ? 1.5 +5 lsb differential nonlinearity ? 1.0 +3 lsb analog output (for ir and 2r gain setting modes) offset error ?.02 0.01 +0.02 % of fsr gain error (with internal reference) ?.0 +1.0 % of fsr gain matching ?.0 0.1 +1.0 % of fsr full-scale output current 2 220ma output compliance range ?.0 +1.25 v output resistance 200 k ? output capacitance 3 pf gain, offset cal dacs, monotonicity guaranteed reference output reference voltage 1.14 1.20 1.26 v reference output current 3 100 na reference input input compliance range 0.1 1.25 v reference input resistance (reflo = 3 v) 10 m ? small signal bandwidth 0.5 mhz temperature coefficients offset drift 0 ppm of fsr/ c gain drift (with internal reference) 50 ppm of fsr/ c reference voltage drift ppm/ c power supply avdd voltage range 3.1 3.3 3.5 v analog supply current (i avdd ) 4 72.5 76 ma i avdd in sleep mode 23.3 26 ma clkvdd voltage range 3.1 3.3 3.5 v clock supply current (i clkvdd ) 4 8.5 ma clkvdd (pll on) clock supply current (i clkvdd )23.5ma dvdd voltage range 3.1 3.3 3.5 v digital supply current (i dvdd ) 4 34 41 ma nominal power dissipation 380 410 mw p dis 5 1.75 w p dis in pwdn 6.0 mw power supply rejection ratio?vdd 0.4 % of fsr/v operating range ?0 +85 c notes 1 measured at i outa driving a virtual ground. 2 nominal full-scale current, i outfs , is 32 the i ref current. 3 use an external amplifier to drive any external load. 4 100 msps f dac with f out = 1 mhz, all supplies = 3.3 v, no interpolation, no modulation. 5 400 msps f dac = 50 msps, f s /2 modulation, pll enabled. specifications subject to change without notice. (t min to t max , avdd = 3.3 v, clkvdd = 3.3 v, dvdd = 3.3 v, pllvdd = 3.3 v, i outfs = 20 ma, unless otherwise noted.) ad9775?pecifications
rev. 0 C4C ad9775 dynamic specifications (t min to t max , avdd = 3.3 v, clkvdd = 3.3 v, dvdd = 3.3 v, pllvdd = 0 v, i outfs = 20 ma, interpolation = 2 , differential transformer coupled output, 50 doubly terminated, unless otherwise noted.) parameter min typ max unit dynamic performance maximum dac output update rate (f dac ) 400 msps output settling time (t st ) (to 0.025%) 11 ns output rise time (10% to 90%) * 0.8 ns output fall time (10% to 90%) * 0.8 ns output noise (i outfs = 20 ma) 50 pa hz ac linearity?aseband mode spurious-free dynamic range (sfdr) to nyquist (f out = 0 dbfs) f data = 100 msps, f out = 1 mhz 71 84.5 dbc f data = 65 msps, f out = 1 mhz 84 dbc f data = 65 msps, f out = 15 mhz 80 dbc f data = 78 msps, f out = 1 mhz 84 dbc f data = 78 msps, f out = 15 mhz 80 dbc f data = 160 msps, f out = 1 mhz 82 dbc f data = 160 msps, f out = 15 mhz 80 dbc spurious-free dynamic range within a 1 mhz window (f out = 0 dbfs, f data = 100 msps, f out = 1 mhz) 73 91.3 dbc two-tone intermodulation (imd) to nyquist (f out1 = f out2 = ? dbfs) f data = 65 msps, f out1 = 10 mhz; f out2 = 11 mhz 81 dbc f data = 65 msps, f out1 = 20 mhz; f out2 = 21 mhz 76 dbc f data = 78 msps, f out1 = 10 mhz; f out2 = 11 mhz 81 dbc f data = 78 msps, f out1 = 20 mhz; f out2 = 21 mhz 76 dbc f data = 160 msps, f out1 = 10 mhz; f out2 = 11 mhz 81 dbc f data = 160 msps, f out1 = 20 mhz; f out2 = 21 mhz 76 dbc total harmonic distortion (thd) f data = 100 msps, f out = 1 mhz; 0 dbfs ?1 ?2.5 db signal-to-noise ratio (snr) f data = 78 msps, f out = 5 mhz; 0 dbfs 76 db f data = 160 msps, f out = 5 mhz; 0 dbfs 74 db adjacent channel power ratio (aclr) wcdma with 3.84 mhz bw, 5 mhz channel spacing if = baseband, f data = 76.8 msps 75 dbc if = 19.2 mhz, f data = 76.8 msps 73 dbc four-tone intermodulation 21 mhz, 22 mhz, 23 mhz, and 24 mhz at ?2 dbfs 75 dbfs (f data = msps, missing center) ac linearity?f mode four-tone intermodulation at if = 200 mhz mhz, mhz, mhz, and mhz at dbfs 72 dbfs (f data = msps, f dac = mhz) * measured single-ended into 50 ? load. specifications subject to change without notice.
rev. 0 C5C ad9775 digital specifications (t min to t max , avdd = 3.3 v, clkvdd = 3.3 v, pllvdd = 0 v, dvdd = 3.3 v, i outfs = 20 ma, unless otherwise noted.) parameter min typ max unit digital inputs logic ??voltage 2.1 3 v logic ??voltage 0 0.9 v logic ??current ?0 +10 a logic ??current ?0 +10 a input capacitance 5 pf clock inputs input voltage range 0 3 v common-mode voltage 0.75 1.5 2.25 v differential voltage 0.5 1.5 v specifications subject to change without notice. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9775 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings * parameter with respect to min max unit avdd, dvdd, clkvdd agnd, dgnd, clkgnd ?.3 +4.0 v avdd, dvdd, clkvdd avdd, dvdd, clkvdd ?.0 +4.0 v agnd, dgnd, clkgnd agnd, dgnd, clkgnd ?.3 +0.3 v refio, reflo, fsadj1/2 agnd ?.3 avdd + 0.3 v i outa , i outb agnd ?.0 avdd + 0.3 v p1b13?1b0, p2b13?2b0 dgnd ?.3 dvdd + 0.3 v dataclk, pll_lock dgnd ?.3 dvdd + 0.3 v clk+, clk? reset clkgnd ?.3 clkvdd + 0.3 v lpf clkgnd ?.3 clkvdd + 0.3 v spi_csb, spi_clk, dgnd ?.3 dvdd + 0.3 v spi_sdio, spi_sdo junction temperature +125 c storage temperature ?5 +150 c lead temperature (10 sec) +300 c * stresses above those listed under the absolute maximum ratings may cause permanent damage to the device. this is a stress ratin g only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specificatio n is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. ordering guide temperature package package model range description option * ad9775bsv ?0 c to +85 c 80-lead tqfp sv-80 AD9775EB evaluation board * sv = thin plastic quad flatpack thermal characteristics thermal resistance 80-lead thermally enhanced tqfp package ja = 23.5 c/w * * with thermal pad soldered to pcb.
rev. 0 ad9775 C6C pin configuration 80 79 78 77 76 71 70 69 68 67 66 65 75 74 73 72 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 12 17 18 20 19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 pin 1 identifier top view (not to scale) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 nc = no connect avdd agnd avdd agnd avdd agnd agnd i outa1 i outb1 agnd agnd i outa2 i outb2 agnd agnd avdd agnd avdd agnd avdd clkvdd lpf clkvdd clkgnd clk+ clk dataclk/pll_lock dgnd dvdd p1b13 (msb) p1b12 p1b11 p1b10 p1b9 p1b8 dgnd dvdd p1b7 p1b6 fsadj1 fsadj2 refio reset spi_csb spi_clk spi_sdio spi_sdo dgnd dvdd nc nc p2b0 (lsb) p2b1 p2b2 p2b3 p1b5 p1b4 p1b3 p1b2 dgnd dvdd p1b1 p1b0 (lsb) nc nc oneportclk/p2b12 p2b11 p2b10 dgnd dvdd iqsel/p2b13 (msb) ad9775 txdac+ dgnd dvdd p2b4 p2b5 p2b9 p2b8 p2b7 p2b6 clkgnd
rev. 0 ad9775 C7C pin function descriptions pin number mnemonic description 1, 3 clkvdd clock supply voltage 2 lpf pll loop filter 4, 7 clkgnd clock supply common 5 clk+ differential clock input 6 clk differential clock input 8 dataclk/pll_lock with the pll enabled, this pin indicates the state of the pll. a read of a logic ??indicates the pll is in the locked state. logic ??indicates the pll has not achieved lock. this pin may also be programmed to act as either an input or output (address 02h, bit 3) dataclk signal running at the input data rate. 9, 17, 25, 35, 44, 52 dgnd digital common 10, 18, 26, 36, 43, 51 dvdd digital supply voltage 11?6, 19?4, 27, 28 p1b13 (msb) to p1b0 (lsb) port ??data inputs 29, 30, 49, 50 nc no connect 31 iqsel/p2b13 (msb) in ??port mode, iqsel = 1 followed by a rising edge of the differential input clock will latch the data into the i channel input register. iqsel = 0 will latch the data into the q channel input register. in ??port mode, this pin becomes the port ??msb. 32 oneportclk/p2b12 with the pll disabled and the ad9775 in ??port mode, this pin becomes a clock output that runs at twice the input data rate of the i and q channels. this allows the ad9775 to accept and demux interleaved i and q data to the i and q input registers. 33, 34, 37?2, 45?8 p2b11 to p2b0 (lsb) port ??data inputs 53 spi_sdo in the case where sdio is an input, sdo acts as an output. when sdio becomes an output, sdo enters a high-z state. 54 spi_sdio bidirectional data pin. data direction is controlled by bit 7 of register address 00h. the default setting for this bit is ?,?which sets sdio as an input. 55 spi_clk data input to the spi port is registered on the rising edge of spi_clk. data output on the spi port is registered on the falling edge. 56 spi_csb chip select/spi data synchronization. on momentary logic high, resets spi port logic and initializes instruction cycle. 57 reset logic ??resets all of the spi port registers, including address 00h, to their default values. a software reset can also be done by writing a logic ??to spi register 00h, bit 5. however, the software reset has no effect on the bits in address 00h. 58 refio reference output, 1.2 v nominal 59 fsadj2 full-scale current adjust, q channel 60 fsadj1 full-scale current adjust, i channel 61, 63, 65, 76, 78, 80 avdd analog supply voltage 62, 64, 66, 67, 70, 71, agnd analog common 74, 75, 77, 79 68, 69 i outa2 , i outb2 differential dac current outputs, q channel 72, 73 i outa1 , i outb1 differential dac current outputs, i channel
rev. 0 ad9775 C8C digital filter specifications half-band filter no. 1 (43 coefficients) tap coefficient 1, 43 8 2, 42 0 3, 41 ?9 4, 40 0 5, 39 67 6, 38 0 7, 37 ?34 8, 36 0 9, 35 244 10, 34 0 11, 33 ?14 12, 32 0 13, 31 673 14, 30 0 15, 29 ?079 16, 28 0 17, 27 1772 18, 26 0 19, 25 ?280 20, 24 0 21, 23 10364 22 16384 half-band filter no. 2 (19 coefficients) tap coefficient 1, 19 19 2, 18 0 3, 17 ?20 4, 16 0 5, 15 438 6, 14 0 7, 13 ?288 8, 12 0 9, 11 5047 10 8192 half-band filter no. 3 (11 coefficients) tap coefficient 1, 11 7 2, 10 0 3, 9 ?3 4, 8 0 5, 7 302 6 512 f out ?normalized to input data rate ?20 0 0.5 attenuation ?dbfs ?00 ?0 ?0 ?0 ?0 0 20 1.0 1.5 2.0 figure 1a. 2 interpolating filter response f out ?normalized to input data rate ?20 0 0.5 attenuation ?dbfs ?00 ?0 ?0 ?0 ?0 0 20 1.0 1.5 2.0 figure 1b. 4 interpolating filter response f out ?normalized to input data rate ?20 02 attenuation ?dbfs ?00 ?0 ?0 ?0 ?0 0 20 468 figure 1c. 8 interpolating filter response
rev. 0 ad9775 C9C definitions of specifications adjacent channel power ratio (acpr) a ratio in dbc between the measured power within a channel relative to its adjacent channel. complex image rejection in a traditional two-part upconversion, two images are created around the second if frequency. these images are redundant and have the effect of wasting transmitter power and system bandwidth. by placing the real part of a second complex modu- lator in series with the first complex modulator, either the upper or lower frequency image near the second if can be rejected. complex modulation the process of passing the real and imaginary components of a signal through a complex modulator (transfer function = e j t = cos t + jsin t) and realizing real and imaginary components on the modulator output. differential nonlinearity (dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to ?,?minus the output when all inputs are set to ?. glitch impulse asymmetrical switching times in a dac give rise to undesired output transients that are quantified by a glitch impulse. it is specified as the net area of the glitch in pv ? . group delay number of input clocks between an impulse applied at the device input and peak dac output current. a half-band fir filter has constant group delay over its entire frequency range. impulse response response of the device to an impulse applied to the input. interpolation filter if the digital inputs to the dac are sampled at a multiple rate of f data (interpolation rate), a digital filter can be constructed with a sharp transition band near f data /2. images that would typically appear around f dac (output data rate) can be greatly suppressed. linearity error (also called integral nonlinearity or inl) linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. monotonicity a d/a converter is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of 0 is called offset error. for i outa , 0 ma output is expected when the inputs are all ?.?for i outb , 0 ma output is expected when all inputs are set to ?. output compliance range the range of allowable voltage at the output of a current output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. pass band frequency band in which any input applied therein passes unattenuated to the dac output. power supply rejection the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. settling time the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. spurious-free dynamic range the difference, in db, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. stop-band rejection the amount of attenuation of a frequency outside the pass band applied to the dac, relative to a full-scale signal applied at the dac input within the pass band. temperature drift temperature drift is specified as the maximum change from the ambient (25 c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full-scale range (fsr) per c. for reference drift, the drift is reported in ppm per c. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured fundamental. it is expressed as a percentage or in decibels (db).
rev. 0 ad9775 C10C frequency ?mhz amplitude ?dbm ?0 0 65 130 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 10 tpc 1. single-tone spec- trum @ f data = 65 msps with f out = f data /3 frequency ?mhz amplitude ?dbm ?0 0 50 150 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 10 100 tpc 4. single-tone spec- trum @ f data = 78 msps with f out = f data /3 frequency ?mhz amplitude ?dbm ?0 0 100 300 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 10 200 tpc 7. single-tone spec- trum @ f data = 160 msps with f out = f data /3 frequency ?mhz sfdr ?dbc 50 0 20 30 55 60 65 70 75 80 85 90 10 15 25 5 ?2dbfs ?dbfs 0dbfs tpc 2. in-band sfdr vs. f out @ f data = 65 msps frequency ?mhz sfdr ?dbc 50 0 20 30 55 60 65 70 75 80 85 90 10 15 25 5 ?dbfs ?2dbfs 0dbfs tpc 5. in-band sfdr vs. f out @ f data = 78 msps frequency ?mhz sfdr ?dbc 50 0 20 30 55 60 65 70 75 80 85 90 10 ?dbfs ?2dbfs 0dbfs 40 50 tpc 8. in-band sfdr vs. f out @ f data = 160 msps frequency ?mhz sfdr ?dbc 50 0 20 30 55 60 65 70 75 80 85 90 10 15 25 5 ?2dbfs 0dbfs ?dbfs tpc 3. out-of-band sfdr vs. f out @ f data = 65 msps frequency ?mhz sfdr ?dbc 50 0 20 30 55 60 65 70 75 80 85 90 10 15 25 5 ?2dbfs 0dbfs ?dbfs tpc 6. out-of-band sfdr vs. f out @ f data = 78 msps frequency ?mhz sfdr ?dbc 50 0 20 30 55 60 65 70 75 80 85 90 10 ?dbfs ?2dbfs 0dbfs 40 50 tpc 9. out-of-band sfdr vs. f out @ f data = 160 msps ? ypical performance characteristics (t = 25 c, avdd = 3.3 v, clkvdd = 3.3 v, dvdd = 3.3 v, i outfs = 20 ma, interpolation = 2 , differential coupled transformer output, 50 doubly terminated, unless otherwise noted.)
rev. 0 C11C ad9775 frequency ?mhz imd ?dbc 50 0 20 30 55 60 65 70 75 80 85 90 10 15 25 5 0dbfs ?dbfs ?dbfs tpc 10. third order imd products vs. f out @ f data = 65 msps frequency ?mhz imd ?dbc 50 0 40 60 55 60 65 70 75 80 85 90 20 8 4 1 2 30 55 10 tpc 13. third order imd products vs. f out and interpolation rate, 1 f data = 160 msps, 2 f data = 160 msps, 4 f data = 80 msps, 8 f data = 50 msps avdd ?v sfdr ?dbc 50 3.5 55 60 65 70 75 80 85 90 0dbfs 3.4 3.3 3.2 3.1 ?dbfs ?dbfs tpc 16. third order imd products vs. avdd @ f out = 10 mhz, f dac = 320 msps, f data = 160 msps frequency ?mhz imd ?dbc 50 0 20 30 55 60 65 70 75 80 85 90 10 15 25 5 ?dbfs 0dbfs ?dbfs tpc 11. third order imd products vs. f out @ f data = 78 msps a out ?dbfs imd ?dbc 50 ? 0 55 60 65 70 75 80 85 90 ?0 8 4 1 2 ?5 tpc 14. third order imd products vs. a out and inter- polation rate f data = 50 msps for all cases, 1 f dac = 50 msps, 2 f dac = 100 msps, 4 f dac = 200 msps, 8 f dac = 400 msps snr ?db 55 60 65 70 75 80 85 90 input data rate ?msps 050 150 100 50 pll on pll off tpc 17. snr vs. data rate for f out = 5 mhz frequency ?mhz imd ?dbc 50 0 40 60 55 60 65 70 75 80 85 90 20 30 50 10 ?dbfs 0dbfs ?dbfs tpc 12. third order imd products vs. f out @ f data = 160 msps avdd ?v sfdr ?dbc 50 3.5 55 60 65 70 75 80 85 90 0dbfs 3.4 3.3 3.2 3.1 ?dbfs ?2dbfs tpc 15. sfdr vs. avdd @ f out = 10 mhz, f dac = 320 msps, f data = 160 msps temperature ? c sfdr ?dbc 90 85 50 ?0 0 100 50 70 65 55 60 80 75 fdata = 65msps 160msps 78msps tpc 18. sfdr vs. temperature @ f out = f data /11 (t = 25 c, avdd = 3.3 v, clkvdd = 3.3 v, dvdd = 3.3 v, i outfs = 20 ma, interpolation = 2 , differential coupled transformer output, 50 doubly terminated, unless otherwise noted.)
rev. 0 ad9775 C12C frequency ?mhz amplitude ?dbm 0 ?0 ?00 050 150 100 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 tpc 19. single-tone spuri- ous performance, f out = 10 mhz, f data = 150 msps, no interpolation frequency ?mhz amplitude ?dbm 0 ?0 ?00 05 50 10 15 20 25 30 35 40 45 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 tpc 22. two-tone imd per- formance, f data = 150 msps, interpolation = 4 frequency ?mhz amplitude ?dbm 0 ?0 ?00 0 100 400 200 300 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 tpc 25. single-tone spuri- ous performance, f out = 10 mhz, f data = 50 msps, interpolation = 8 frequency ?mhz amplitude ?dbm 0 ?0 ?00 010 50 20 30 40 ?0 ?0 ?0 tpc 20. two-tone imd per- formance, f data = 150 msps, no interpolation frequency ?mhz amplitude ?dbm 0 ?00 050 300 100 150 200 250 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 tpc 23. single-tone spuri- ous performance, f out = 10 mhz, f data = 80 msps, interpolation = 4 0 frequency ?mhz amplitude ?dbm ?20 020 80 40 60 ?0 ?0 ?0 ?00 ?0 tpc 26. eight-tone imd performance, f data = 160 msps, interpolation = 8 frequency ?mhz amplifier ?dbm 0 ?00 050 300 100 150 200 250 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 tpc 21. single-tone spuri- ous performance, f out = 10 mhz, f data = 150 msps, interpolation = 2 frequency ?mhz amplitude ?dbm 0 ?0 ?00 05 25 10 15 20 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 tpc 24. two-tone imd per- formance, f out = 10 mhz, f data = 50 msps, interpola- tion = 8 (t = 25 c, avdd = 3.3 v, clkvdd = 3.3 v, dvdd = 3.3 v, i outfs = 20 ma, interpolation = 2 , differential coupled transformer output, 50 doubly terminated, unless otherwise noted.)
rev. 0 ad9775 C13C mode control (via spi port) table i. mode control via spi port (default values are highlighted) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h sdio lsb, msb first software reset on sleep mode power-down mode 1r/2r mode pll_lock bidirectional 0 = msb logic ? logic ??shuts down logic ??shuts down dac output current set indicator 0 = input 1 = lsb the dac output all digital and analog by one or two external 1 = i/o currents. functions. resistors. 0 = 2r , 1 = 1r 01h filter filter modulation modulation mode 0 = no zero stuffing 1 = real mix mode 0 = e ? dataclk/ interpolation interpolation mode ( none , f s /2, f s /4, f s /8) on interpolation 0 = complex 1 = e +j pll_lock rate rate ( none , f s /2, filters , logic ? mix mode select (1 , 2 , 4 , 8 )(1 , 2 , 4 , 8 )f s /4, f s /8) enables zero stuffing. 0 = plllock 1 = dataclk 02h 0 = signed input 0 = two port mode dataclk driver dataclk invert oneportclk invert iqsel invert q first data 1 = one port mode strength 0 = no invert 0 = no invert 0 = no invert 0 = i first 1 = unsigned 1 = invert 1 = invert 1 = invert 1 = q first 03h pll divide pll divide (prescaler) ratio (prescaler) ratio 04h 0 = pll off 0 = automatic pll charge pump pll charge pump pll charge pump 1 = pll on charge pump control control control control 1 = programmable 05h idac fine gain idac fine gain idac fine gain idac fine gain idac fine gain idac fine gain idac fine gain idac fine gain adjustment adjustment adjustment adjustment adjustment adjustment adjustment adjustment 06h idac coarse gain idac coarse gain idac coarse gain idac coarse gain adjustment adjustment adjustment adjustment 07h idac offset idac offset idac offset idac offset idac offset idac offset idac offset idac offset adjustment bit 9 adjustment bit 8 adjustment bit 7 adjustment bit 6 adjustment bit 5 adjustment bit 4 adjustment bit 3 adjustment bit 2 08h idac i offset idac offset idac offset direction adjustment bit 1 adjustment bit 0 0 = i offset on i outa 1 = i offset on i outb 09h qdac fine gain qdac fine gain qdac fine gain qdac fine gain qdac fine gain qdac fine gain qdac fine gain qdac fine gain adjustment adjustment adjustment adjustment adjustment adjustment adjustment adjustment 0ah qdac coarse qdac coarse qdac coarse qdac coarse gain adjustment gain adjustment gain adjustment gain adjustment 0bh qdac offset qdac offset qdac offset qdac offset qdac offset qdac offset qdac offset qdac offset adjustment bit 9 adjustment bit 8 adjustment bit 7 adjustment bit 6 adjustment bit 5 adjustment bit 4 adjustment bit 3 adjustment bit 2 0ch qdac i offset qdac offset qdac offset direction adjustment bit 1 adjustment bit 0 0 = i offset on i outa 1 = i offset on i outb 0dh version register version register version register version register
rev. 0 ad9775 C14C register description address 00h bit 7 logic ??(default). causes the sdio pin to act as an input during the data transfer (phase 2) of the communications cycle. when set to ?,?sdio can act as an input or output, depending on bit 7 of the instruction byte. b it 6 logic ??(default). determines the direction (lsb/msb first) of the communications and data transfer communications cycles. refer to the section msb/lsb transfers for a detailed description. bit 5 writing a ??to this bit resets the registers to their default values and restarts the chip. the reset bit always reads back ?.?register address 00h bits are not cleared by this software reset. however, a high level at the reset pin forces all registers, including those in address 00h, to their default state. bit 4 sleep mode. a logic ??to this bit shuts down the dac output currents. bit 3 power-down. logic ??shuts down all analog and digital functions except for the spi port. bit 2 1r/2r mode. the default (?? places the ad9775 in two resistor mode. in this mode, the i ref currents for the i and q dac references are set sepa rately by the r set resistors on fsadj1 and fsadj2 (pins 59 and 60). in the 2r mode, assuming the coarse gain setting is full scale and the fine gain setting is zero, i fullscale1 = 32 v ref /fsadj1 and i fullscale2 = 32 v ref /fsadj2. with this bit set to ?,?the reference currents for both i and q dacs are controlled by a single resistor on pin 60. i fullscale in one resistor mode for both of the i and q dacs is half of what it would be in the 2r mode, assuming all other conditions (r set , register settings) remain unchanged. the full-scale current of each dac can still be set to 20 ma by choosing a resistor of half the value of the r set value used in the 2r mode. bit 1 pll_lock indicator. when the pll is enabled, reading this bit will give the status of the pll. a logic ??indicates the pll is locked. a logic ? indicates an unlocked state. address 01h bits 7, 6 filter interpolation rate according to the follow- ing table: 00 1 01 2 10 4 11 8 bits 5, 4 modulation mode according to the following table: 00 none 01 f s /2 10 f s /4 11 f s /8 bit 3 logic ??enables zero stuffing mode for interpo- lation filters. bit 2 default (?? enables the real mix mode. the i and q data channels are individually modulated by f s /2, f s /4, or f s /8 after the interpolation filters. how ever, no complex modulation is done. in the complex mix mode (logic ??, the digital modulators on the i and q data channels are coupled to create a digi- tal complex modulator. when the ad9775 is applied in conjunction with an external quadrature modulator, rejection can be achieved of either the higher or lower frequency image around the second if frequency (i.e., the second if frequency is the lo of the analog quadrature modulator external to the ad9775) according to the bit value of register 01h, bit 1. bit 1 logic ??(default) causes the complex modulation to be of the form e ? t , resulting in the rejection of the higher frequency image when the ad9775 is used with an external quadrature modulator. a logic ? causes the modulation to be of the form e +j t , which causes rejection of the lower frequency image. bit 0 in two port mode, a logic ??(default) causes pin 8 to act as a lock indicator for the internal pll. a logic ??in this register causes pin 8 to act as a dataclk, either generating or acting as an input clock (see register 02h, bit 3) at the input data rate of the ad9775. address 02h bit 7 logic ??(default) causes data to be accepted on the inputs as two? complement binary. logic ? causes data to be accepted as straight binary. bit 6 logic ??(default) places the ad9775 in two port mode. i and q data enters the ad9775 via ports 1 and 2, respectively. a logic ??places the ad9775 in one port mode in which interleaved i and q data is applied to port 1. see the pin function de scrip- tions for dataclk/pll_lock, iqsel, and oneportclk for detailed information on how to use these modes. bit 5 dataclk driver strength. with the internal pll disabled, and this bit set to logic ?,?it is recom- mended that dataclk be buffered. when this bit is set to logic ?,?dataclk acts as a stronger driver capable of driving small capacitive loads. bit 4 default logic ?.?a value of ??inverts dataclk at pin 8. bit 2 default logic ?.?a value of 1 inverts oneportclk at pin 32. bit 1 the default of logic ??causes iqsel = 1 to direct input data to the i channel, while iqsel = 0 directs input data to the q channel. a logic ??in this register inverts the sense of iqsel. bit 0 the default of logic ??defines iq pairing as iq, iq...while programming a logic ??causes the pair ordering to be qi, qi...
rev. 0 ad9775 C15C address 03h bits 1, 0 setting this divide ratio to a higher number allows the vco in the pll to run at a high rate (for best performance) while the dac input and output clocks run substantially slower. the divider ratio is set according to the following table: 00 1 01 2 10 4 11 8 address 04h bit 7 logic ??(default) disables the internal pll. logic ??enables the pll. bit 6 logic ??(default) sets the charge pump control to automatic. in this mode, the charge pump bias current is controlled by the divider ratio defined in address 03h, bits 1 and 0. logic ??allows the user to manually define the charge pump bias cur- rent using address 04h, bits 2, 1, and 0. adjusting the charge pump bias current allows the user to optimize the noise/settling performance of the pll. bits 0, 1, 2 with the charge pump control set to manual, these bits define the charge pump bias current according to the following table: 000 50 a 001 100 a 010 200 a 011 400 a 100 800 a address 05h, 09h bits 7? these bits represent an 8-bit binary number (bit 7 msb) that defines the fine gain adjustment of the i (05h) and q (09h) dac, according to the equation given below. address 06h, 0ah bits 3? these bits represent a 4-bit binary number (bit 3 msb) that defines the coarse gain adjustment of the i (06h) and q (0ah) dacs according to the equation below. address 07h, 0bh bits 7? address 08h, 0ch bit 1, 0 the 10 bits from these two address pairs (07h, 08h and 0bh, 0ch) represent a 10-bit binary number that defines the offset adjustment of the i and q dacs according to the equation below (07h, 0bh?it 7 msb/08h, 0ch?it 0 lsb) address 08h, 0ch bit 7 this bit determines the direction of the offset of the i (08h) and q (0ch) dacs. a logic ??will apply a positive offset current to i outa , while a logic ? will apply a positive offset current to i outb . the magnitude of the offset current is defined by the bits in addresses 07h, 0bh, 08h, and 0ch accord- ing to the formulas given below. i i coarse i fine data i i coarse i fine outa ref ref outb ref ref = ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? 6 8 1 16 3 32 256 1024 24 2 6 8 1 16 3 32 256 14 ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? 1024 24 21 2 4 1024 14 14 data ii offset offset ref (1) equation 1 shows i outa and i outb as a function of fine gain, coarse gain, and offset adjustment when using the 2r mode. in the 1r mode, the current i ref is created by a single fsadj resistor (pin 60). this current is divided equally into each channel so that a scaling factor of one-half must be added to these equations for full-scale currents for both dacs and the offset.
rev. 0 ad9775 C16C functional description the ad9775 dual interpolating dac consists of two data chan- nels that can be operated completely independently or coupled to form a complex modulator in an image reject transmit archi tec- ture. each channel includes three fir filters, making the ad9775 capable of 2 , 4 , or 8 interpolation. high speed input and output data rates can be achieved within the following limi tations. interpolation input data dac sample rate (msps) rate (msps) rate (msps) 1 160 160 2 160 320 4 100 400 8 50 400 both data channels contain a digital modulator capable of mix- ing the data stream with an lo of f dac /2, f dac /4, or f dac /8, where f dac is the output data rate of dac. a zero stuffing fea- ture is also included and can be used to improve pass-band flatness for signals being attenuated by the sin(x)/x characteristic of the dac output. the speed of the ad9775, combined with the digital modulation capability, enables direct if conversion architectures at 70 mhz and higher. the digital modulators on the ad9775 can be coupled to form a complex modulator. by using this feature with an external analog quadrature modulator, such as analog devices?ad8345, an image rejection architecture can be enabled. to optimize the image rejection capability, as well as lo feedthrough in this architecture, the ad9775 offers programmable (via the spi port) gain and offset adjust for each dac. also included on the ad9775 are a phase-locked loop (pll) clock multiplier and a 1.20 v band gap voltage reference. with the pll enabled, a clock applied to the clk+/clk?inputs is frequency multiplied internally and generates all necessary internal synchronization clocks. each 14-bit dac provides two com ple mentary current outputs whose full-scale currents can be determined either from a single external resistor or indepen- dently from two separate resistors (see 1r/2r mode). the ad9775 features a low jitter, differential clock input that provides excellent noise rejection while accepting a sine or square w ave input. separate voltage supply inputs are provided for each functional block to ensure optimum noise and distor- tion performance. sleep and power-down modes can be used to turn off the dac output current (sleep) or the entire digital and analog sections (power-down) of the chip. an spi-compliant serial port is used to program the many features of the ad9775. note that in power-down mode, the spi port is the only section of the chip still active. ad9775 spi port in terface sclk (pin 55) csb (pin 56) sdio (pin 54) sdo (pin 53) figure 2. spi port interface serial interface for register control the ad9775 serial port is a flexible, synchronous serial com- mu n ica tions port allowing easy interface to many industry standard m icrocontrollers and microprocessors. the serial i/o is compatible with most synchronous transfer formats, including both the motorola spi and intel ssr protocols. the interface allows read/write access to all registers that configure the ad9775. single- or multiple-byte transfers are supported as well as msb first or lsb first transfer formats. the ad9775? serial interface port can be configured as a single pin i/o (sdio) or two unidi- rectional pins for in/out (sdio/sdo). general operation of the serial interface there are two phases to a communication cycle with the ad 9775. phase 1 is the instruction cycle, which is the writing of an in struc- tion byte into the ad9775 coincident with the first eight sclk rising edges. the instruction byte provides the ad9775 serial port controller with information regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. the first eight sclk rising edges of each communication cycle are used to write the instruction byte into the ad9775. a logic high on the csb pin, followed by a logic low, will reset the spi port timing to the initial state of the instruction cycle. this is true regardless of the present state of the internal regis- ters or the other signal levels present at the inputs to the spi port. if the spi port is in the midst of an instruction cycle or a data transfer cycle, none of the present data will be written. the remaining sclk edges are for phase 2 of the communica- tion cycle. phase 2 is the actual data transfer between the ad 9775 and the system controller. phase 2 of the communication cycle is a transfer of 1, 2, 3, or 4 data bytes as determined by the instruction byte. normally, using one multibyte transfer is the preferred method. however, single byte data transfers are useful to reduce cpu overhead when register access requires one byte only. registers change immediately upon writing to the last bit of each transfer byte. instruction byte the instruction byte contains the information shown below. n1 n0 description 00 transfer 1 byte 01 transfer 2 bytes 10 transfer 3 bytes 11 transfer 4 bytes
rev. 0 ad9775 C17C r/w bit 7 of the instruction byte determines whether a read or a write data transfer will occur after the instruction byte write. logic high indicates read operation. logic ??indicates a write operation. n1, n0 bits 6 and 5 of the instruction byte determine the number of bytes to be transferred during the data transfer cycle. the bit decodes are shown in the following table: msb lsb i7 i6 i5 i4 i3 i2 i1 i0 r/w n1 n0 a4 a3 a2 a1 a0 a4, a3, a2, a1, a0 bits 4, 3, 2, 1, and 0 of the instruction byte determine which register is accessed during the data transfer portion of the com- munications cycle. for multibyte transfers, this address is the starting byte address. the remaining register addresses are generated by the ad9775. serial interface port pin descriptions sclk (pin 55)?erial clock the serial clock pin is used to synchronize data to and from the ad9775 and to run the internal state machines. sclk maxi- mum frequency is 15 mhz. all data input to the ad9775 is registered on the rising edge of sclk. all data is driven out of the ad9775 on the falling edge of sclk. csb (pin 56)?hip select active low input starts and gates a communication cycle. it allows more than one device to be used on the same serial com- munications lines. the sdo and sdio pins will go to a high impedance state when this input is high. chip select should stay low during the entire communication cycle. sdio (pin 54)?erial data i/o data is always written into the ad9775 on this pin. however, this pin can be used as a bidirectional data line. the configura- tion of this pin is controlled by bit 7 of register address 00h. the default is logic ?,?which configures the sdio pin as unidirectional. sdo (pin 53)?erial data out data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case where the ad 9775 operates in a single bidirectional i/o mode, this pin does not output data and is set to a high impedance state. msb/lsb transfers the ad9775 serial port can support both most significant bit (msb) first or least significant bit (lsb) first data formats. this functionality is controlled by register address 00h, bit 6. the default is msb first. when this bit is set active high, the ad 9775 serial port is in lsb first format. that is, if the ad9775 is in lsb first mode, the instruction byte must be written from least- significant bit to most significant bit. multibyte data transfers in msb format can be completed by writing an instruction byte that includes the register address of the most significant byte. in msb first mode, the serial port internal byte address generator decrements for each byte required of the multibyte communica- tion cycle. multibyte data transfers in lsb first format can be completed by writing an instruction byte that includes the regis- ter address of the least significant byte. in lsb first mode, the serial port internal byte address generator increments for each byte required of the multibyte communication cycle. the ad9775 serial port controller address will increment from 1fh to 00h for multibyte i/o operations if the msb first mode is active. the serial port controller address will decrement from 00h to 1fh for multibyte i/o operations if the lsb first mode is active. cs sclk sdio sdo data transfer cycle instruction cycle r/w d7 n i4 i3 i2 i1 i0 d6 n d7 n d6 n d0 0 d1 0 d2 0 d0 0 d1 0 d2 0 i6 i5 (n) (n) figure 3a. serial register interface timing msb first cs sclk sdio sdo data transfer cycle instruction cycle r/w i6 d7 n i5 i4 i3 i2 i1 i0 d6 n d7 n d6 n d0 0 d1 0 d2 0 d0 0 d1 0 d2 0 (n) (n) figure 3b. serial register interface timing lsb first
rev. 0 ad9775 C18C t ds t sclk t pwh t pwl t ds t dh instruction bit 7 instruction bit 6 cs sclk sdio figure 4. timing diagram for register write to ad9775 t dv data bit n data bit n? cs sclk sdio sdo figure 5. timing diagram for register read from ad9775 notes on serial port operation the ad9775 serial port configuration bits reside in bits 6 and 7 of register address 00h. it is important to note that the con figura- tion changes immediately upon writing to the last bit of the register. for multibyte transfers, writing to this register may occur dur- ing the middle of the communication cycle. care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. the same considerations apply to setting the reset bit in register address 00h. all other registers are set to their default values, but the software reset doesn? affect the bits in register address 00h. it is recommended to use only single-byte transfers when chang- ing serial port configurations or initiating a software reset. a write to bits 1, 2, and 3 of address 00h with the same logic levels as for bits 7, 6, and 5 (bit pattern: xy1001yx binary) allows the user to reprogram a lost serial port configuration and to reset the registers to their default values. a second write to address 00h with reset bit low and serial port configuration as specified above (xy) reprograms the osc in multiplier set- ting. a changed f sysclk frequency is stable after a maximum of 200 f mclk cycles (equals wake-up time). dac operation the dual 14-bit dac output of the ad9775, along with the reference circuitry, gain, and offset registers, is shown in fig ure 6. referring to the transfer functions in equation 1, a reference current is set by the internal 1.2 v reference, the external r set resistor, and the values in the coarse gain register. the fine gain dac subtracts a small amount from this and the result is input to idac and qdac, where it is scaled by an amount equal to 1024/24. figures 7a and 7b show the scaling effect of the coarse and fine adjust dacs. idac and qdac are pmos current source arrays, segmented in a 5-4-5 configuration. the five most significant bits control an array of 31 current sources. the next four bits consist of 15 current sources whose values are all equal to 1/16 of an msb current source. the five lsbs are binary weighted fractions of the middle bit? current sources. all current sources are switched to either i outa or i outb , de pend- ing on the input code. the fine adjustment of the gain of each channel allows for improved balance of qam modulated signals, resulting in improved modulation accuracy and image rejection. in the applications section of this data sheet, performance data is in cluded that shows to what degree image rejection can be im- proved when the ad9775 is used with an ad8345 quadrature modulator from adi.
rev. 0 ad9775 C19C the offset control defines a small current that can be added to i outa or i outb (not both) on the idac and qdac. the selec- tion of which i out this offset current is directed toward is programmable via register 08h, bit 7 (idac) and register 0ch, bit 7 (qdac). figure 8 shows the scale of the offset current that can be added to one of the complementary outputs on the idac and qdac. offset control can be used for suppression of lo leakage resulting from modulation of dc signal components. if the ad9775 is dc-coupled to an external modulator, this feature can be used to cancel the output offset on the ad9775 as well as the input offset on the modulator. figure 9 shows a typical example of the effect that the offset control has on lo suppression. offset dac qdac idac offset dac refio 0.1 f fsadj1 fsadj2 rset1 rset2 i outa1 i outb1 o ffset c ontrol re gisters i outa2 i outb2 g ain c ontrol re gisters coarse gain dac coarse gain dac fine gain dac fine gain dac 1.2vref g ain c ontrol re gisters o ffset c ontrol re gisters figure 6. dac outputs, reference current scaling, and gain/offset adjust coarse gain register code ?assuming rset1, 2 = 1.9k 05 coarse reference current ?ma 0 25 10 15 20 5 10 15 20 2r mode 1r mode figure 7a. coarse gain effect on i fullscale fine gain register code ?assuming rset1, 2 = 1.9k 05 fine reference current ?ma ?.0 10 15 20 2r mode 1r mode ?.5 ?.0 ?.5 ?.0 ?.5 0 figure 7b. fine gain effect on i fullscale in figure 9, the negative scale represents an offset added to i outb , while the positive scale represents an offset added to i outa of the respective dac. offset register 1 corresponds to idac, while offset register 2 corresponds to qdac. figure 9 represents the ad9775 syn thesizing a complex signal that is then dc-coupled to an ad8345 quadrature modulator with an lo of 800 mhz. the dc-cou pling allows the input offset of the ad8345 to be calibrated out as w ell. the lo suppression at the ad8345 output was optimized first by adjusting offset register 1 in the ad9775. when an optimal point was found (roughly code 54), this code was held in offset register 1, and offset register 2 was adjusted. the resulting lo suppression is 70 dbfs. these are typical numbers and the specific code for optimization will vary from part to p art. coarse gain register code ?assuming rset1, 2 = 1.9k 0 200 offset current ?ma 0 5 400 600 800 1 2 3 4 2r mode 1r mode 1000 figure 8. dac output offset current
rev. 0 ad9775 C20C offset register 1 adjusted dac1, dac2 ?offset register codes ?024 ?68 lo suppression ?dbfs ?0 0 1024 ?12 ?56 0 256 512 768 ?0 ?0 ?0 ?0 ?0 ?0 ?0 offset register 2 adjusted, with offset register 1 set to optimized value figure 9. offset adjust control, effect on lo suppression 1r/2r mode in the 2r mode, the reference current for each channel is set independently by the fsadj resistor on that channel. the ad9775 can be programmed to derive its reference current from a single resistor on pin 60 by placing the part in the 1r mode. the trans- fer functions in equation 1 are valid for the 2r mode. in the 1r mode, the current developed in the single fsadj resistor is split equally between the two channels. the result is that in the 1r mode, a scale factor of one-half must be applied to the for- mulas in equation 1. the full-scale dac current in the 1r mode can still be set to as high as 20 ma by using the internal 1.2 v reference and a 950 ? resistor, instead of the 1.9 k ? resistor typically used in the 2r mode. clock input configurations the clock inputs to the ad9775 can be driven differentially or single-ended. the internal clock circuitry has supply and ground (clkvdd, clkgnd) separate from the other supplies on the chip to minimize jitter from internal noise sources. figure 10 shows the ad9775 driven from a single-ended clock source. the clk+/clk?pins form a differential input (clkin), so that the statically terminated input must be dc-biased to the midswing voltage level of the clock driven input. r series v threshold ad9775 clk+ clkvdd clk clkgnd 0.1 f figure 10. single-ended clock driving clock inputs a configuration for differentially driving the clock inputs is given in figure 11. dc-blocking capacitors can be used to couple a clock driver output whose voltage swings exceed clkvdd or clkgnd. if the driver voltage swings are within the supply range of the ad9775, the dc-blocking capacitors and bias resistors are not necessary. ad9775 clk+ clkvdd clk clkgnd 0.1 f 1k ecl/pecl 1k 1k 1k 0.1 f 0.1 f figure 11. differential clock driving clock inputs a transformer, such as the t1-1t from mini-circuits, can also be used to convert a single-ended clock to differential. this method is used on the ad9775 evaluation board so that an exter- nal sine wave with no dc offset can be used as a differential clock. pecl/ecl drivers require varying termination networks, the details of which are left out of figures 10 and 11 but can be found in application notes such as and8020/d from on semiconductor. these networks depend on the assumed transmission line im ped- ance and power supply voltage of the clock driver. optimum performance of the ad9775 is achieved when the driver is placed very close to the ad9775 clock inputs, thereby negating any transmission line effects such as reflections due to mismatch. the quality of the clock and data input signals is important in achieving optimum performance. the external clock driver cir- cuitry should provide the ad9775 with a low jitter clock input that meets the min/max logic levels while providing fast edges. although fast clock edges help minimize any jitter that will manifest itself as phase noise on a reconstructed waveform, the high gain bandwidth product of the ad9775? differential comparator can tolerate sine wave inputs as low as 0.5 v p-p, with minimal degradation of the output noise floor. programmable pll clkin can function either as an input data rate clock (pll enabled) or as a dac data rate clock (pll disabled) according to the state of address 02h, bit 7 in the spi port register. the internal operation of the ad9775 clock circuitry in these two modes is illustrated in figures 12 and 13. the pll clock multiplier and distribution circuitry produce the necessary internal synchronized 1 , 2 , 4 , and 8 clocks for the rising edge triggered latches, interpolation filters, modula- tors, and dacs. this circuitry consists of a phase detector, charge pump, voltage controlled oscillator (vco), prescaler, clock distribution, and spi port control. the charge pump and vco are powered from pllvdd while the differential clock input buffer, phase detector, prescaler, and clock distribution are powered from clkvdd. pll lock status is indicated by the logic signal at the pll_lock pin, as well as by the status of bit 1, register 00h. to ensure optimum phase noise perform ance from the pll clock multiplier and distribution, pllvdd and clkvdd should originate from the same clean analog supply. the speed of the vco with the pll enabled also has an effect on phase noise. optimal phase noise with respect to vco speed is achieved by running the vco in the range of 450 mhz to 550 mhz. the vco speed is a function of the input data rate, the interpolation rate, and the vco prescaler, according to the following function: vco speed mhz input data rate mhz interpolationrate escaler () () = pr
rev. 0 ad9775 C21C charge pump phase detector clk+ clock distribution circuitry vco ad9775 clk spi port internal spi control registers pll_lock 1 = lock 0 = no lock pllvdd lpf interpolation filters, modulators, and dacs 2 8 interpolation rate control pll divider (pres caler) control pll control ( pll on) 1 input data latches modulation rate control prescaler 4 figure 12. pll and clock circuitry with pll enabled charge pump phase detector clk+ clock distribution circuitry vco ad9775 clk spi port internal spi control registers pll_lock 1 = lock 0 = no lock interpolation filters, modulators, and dacs 2 8 interpolation rate control pll divider (pres caler) control pll control ( pll on) 1 input data latches modulation rate control prescaler 4 figure 13. pll and clock circuitry with pll disabled in addition, if the zero stuffing option is enabled, the vco will double its speed again. phase noise may be slightly higher with the pll enabled. figure 14 illustrates typical phase noise per- formance of the ad9775 with 2 interpolation and various input data rates. the signal synthesized for the phase noise measurement was a single carrier at a frequency of f data /4. the repetitive nature of this signal eliminated quantization noise and distortion spurs as a factor in the measurement. although the curves blend together in figure 14, the different conditions are called out here for clarity. f data pll prescaler ratio 125 msps disabled 125 msps enabled div1 100 msps enabled div2 75 msps enabled div2 50 msps enabled div4 frequency offset ?mhz phase noise ?dbfs ?0 0 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?10 ?00 12345 figure 14. phase noise performance it is important to note that the resistor/capacitor needed for the pll loop filter is internal on the ad9775. this will suffice un less the input data rate is below 10 mhz, in which case an external series rc is required between the lpf and pllvdd pins. power dissipation the ad9775 has three voltage supplies: avdd, dvdd, and clkvdd. figures 15, 16, and 17 show the current required from each of these supplies when each is set to the 3.3 v nominal specified for the ad9775. power dissipation (p d ) can easily be extracted by multiplying the given curves by 3.3. as figure 15 shows, i dvdd is very dependent on the input data rate, the interpo- lation rate, and the activation of the internal digital modulator. i dvdd , however, is relatively insensitive to the modulation rate by itself. in figure 16, i avdd shows the same type of sensitivity to the data, the interpolation rate, and the modulator function but to a m uch lesser degree (<10%). in figure 17, i clkvdd varies over a wide range yet is responsible for only a small per- centage of the overall ad9775 supply current requirements. f data ?mhz 050 i dvdd ?ma 0 100 150 200 50 100 150 200 250 300 350 400 8 (mod. on) , 4 (mod. on) , 2 (mod. on) , 8 4 2 1 figure 15. i dvdd vs. f data vs. interpolation rate, pll disabled
rev. 0 ad9775 C22C f data ?mhz 050 i avdd ?ma 72.0 100 150 200 72.5 8 (mod. on) , 4 (mod. on) , 2 (mod. on) , 8 4 2 1 73.0 73.5 74.0 74.5 75.0 75.5 76.0 figure 16. i avdd vs. f data vs. interpolation rate, pll disabled f data ?mhz 050 i clkvdd ?ma 0 100 150 200 5 10 15 20 25 30 35 8 4 2 1 figure 17. i clkvdd vs. f data vs. interpolation rate, pll disabled sleep/power-down modes (control register 00h, bits 3 and 4) the ad9775 provides two methods for programmable reduc tion in power savings. the sleep mode, when activated, turns off the dac output currents but the rest of the chip remains function ing. when coming out of sleep mode, the ad9775 will immediately return to full operation. power-down mode, on the other hand, turns off all analog and digital circuitry in the ad9775 except for the spi port. when returning from power-down mode, enough clock cycles must be allowed to flush the digital filters of random data acquired during the power-down cycle. one/two port input modes the digital data input ports can be configured as two independent ports or as a single (one port mode) port. in two port mode, the ad9775 can be programmed to generate an externally avail- able data rate clock (dataclk) for the purpose of data synchronization. data at the two input ports can be latched into the ad9775 on every rising clock edge of dataclk. in one port mode, p2b12 and p2b13 from input data port 2 are redefined as iqsel and oneportclk, respectively. the input data in one port mode is steered to one of the two internal data channels based on the logic level of iqsel. a clock signal, oneportclk, is generated by the ad9775 in this mode for the purpose of external data synchronization. oneportclk runs at the input interleaved data rate which is 2 the data rate at the internal input to either channel. test configurations showing the various clocks that are re quired and produced by the ad9775 in the pll and one /two por t modes are given in figures 55 through 58. jumper positions needed to operate the ad9775 evaluation board in these modes are given as well. pll enabled, two port mode (control register 02h, bits 6? and 04h, bits 7?) with the phase-locked loop (pll) enabled and the ad9775 in two port mode, the speed of clkin is inherently that of the input data rate. in two port mode, pin 8 (dataclk/pll_ lock) can be programmed (control register 01h, bit 0) to function as either a lock indicator for the internal pll or as a clock running at the input data rate. when pin 8 is used as a clock output (dataclk), its frequency is equal to that of clkin. data at the input ports is latched into the ad9775 on the rising edge of the clkin. figure 18 shows the delay, t od , inherent between the rising edge of clkin and the rising edge of dataclk, as well as the setup and hold requirements for the data at ports 1 and 2. note that the setup and hold times given in figure 18 are the input data transitions with respect to clkin. t od can vary with clkin speed, pll divider setting, and interpolation rate. it is therefore highly recommended that the input data be synchro- nized to clkin rather than dataclk when the pll is enabled. note that in two port mode (pll enabled or disabled), the data rate at the interpola tion f ilter inputs is the same as the input data rate at ports 1 and 2. the dac output sample rate in two port mode is equal to the clock input rate multiplied by the interpolation rate. if zero stuffing is used, another factor of two must be included to calcu- late the dac sample rate. dataclk inversion (control register 02h, bit 4) by programming this bit, the dataclk signal shown in figure 18 can be inverted. with inversion enabled, t od will refer to the time between the rising edge of clkin and the falling edge of dataclk. no other effect on timing will oc cur.
rev. 0 ad9775 C23C clkin dataclk data at ports 1 and 2 t od t h t s t s = 0.0ns t h = 2.5ns ( typ specs) figure 18. timing requirements in two port input mode, with pll enabled dataclk driver strength (control register 02h, bit 5) the dataclk output driver strength is capable of driving >10 ma into a 330 ? load while providing a rise time of 3 ns. figure 19 shows dataclk driving a 330 ? resistive load at a frequency of 50 mhz. by enabling the drive strength option (control register 02h, bit 5), the amplitude of dataclk under these conditions will be increased by approximately 200 mv. time ?ns 010 frequency ?v ?.5 20 30 40 0 0.5 1.0 1.5 2.0 2.5 3.0 50 delta approx. 2.8ns figure 19. dataclk driver capability into 330 ? at 50 mhz pll enabled, one port mode (control register 02h, bits 6? and 04h, bits 7?) in one port mode, the i and q channels receive their data from an interleaved stream at digital input port 1. the function of pin 32 is defined as an output (oneportclk) that gener ates a clock at th e interleaved data rate which is 2 the internal input data rate of the i and q channels. the frequency of clkin is equal to the internal input data rate of the i and q channels. the selection of the data for the i or the q channel is deter mined by the state of the logic level at pin 31 (iqsel when the ad9775 is in one port mode) on the rising edge of oneportclk. iqsel = 1 under these conditions will latch the data into the i channel on the clock rising edge, while iqsel = 0 will latch the data into the q channel. it is possible to invert the i and q selec tion by set- ting control register 02h, bit 1 to the invert state (logic ??. figure 20 illustrates the timing r equ ire ments for the data inputs as well as the iqsel input. note that the 1 interpolation rate is not available in the one port mode. the dac output sample rate in one port mode is equal to clkin multiplied by the interpolation rate. if zero stuffing is used, another factor of two must be included to calculate the dac sample rate. oneportclk inversion (control register 02h, bit 2) by programming this bit, the oneportclk signal shown in figure 20 can be inverted. with inversion enabled, t od refers to the delay between the rising edge of the external clock and the falling edge of oneportclk. the setup and hold times, t s and t h , will be with respect to the falling edge of onep ortclk. there will be no other effect on timing. oneportclk driver strength the drive capability of oneportclk is identical to that of dataclk in the two port mode. refer to figure 19 for perfor- mance under load conditions. t od t h t s clkin i and q interleaved input data at port 1 oneportclk iqsel t iqh t iqs t od = 4.7ns t s = 3.0ns t h = ?.5ns t iqs = 3.5ns t iqh = ?.5ns figure 20. timing requirements in one port input mode with the pll enabled
rev. 0 ad9775 C24C iq pairing (control register 02h, bit 0) in one port mode, the interleaved data is latched into the ad9775 internal i and q channels in pairs. the order of how the pairs are latched internally is defined by this control register. the following is an example of the effect this has on incoming interleaved data. given the following interleaved data stream, where the data indicates the value with respect to full scale: iqiq iqiqiq 0.5 0.5 1 1 0.5 0.5 0 0 0.5 0.5 with the control register set to ??(i first), the data will appear at the internal channel inputs in the following order in time: i channel 0.5 1 0.5 0 0.5 q channel 0.5 1 0.5 0 0.5 with the control register set to ??(q first), the data will ap pear at the internal channel inputs in the following order in time: i channel 0.5 1 0.5 0 0.5 x q channel y 0.5 1 0.5 0 0.5 the values x and y represent the next i value and the previous q value in the series. pll disabled, two port mode with the pll disabled, a clock at the dac output rate must be applied to clkin. internal clock dividers in the ad9775 syn- thesize the dataclk signal at pin 8, which runs at the input data rate and can be used to synchronize the input data. data is latched into input ports 1 and 2 of the ad9775 on the rising edge of dataclk. dataclk speed is defined as the speed of clkin divided by the interpolation rate. with zero stuffing enabled, this division increases by a factor of 2. figure 21 illustrates the delay between the rising edge of clkin and the rising edge of dataclk, as well as t s and t h in this mode. the programmable modes dataclk inversion and dataclk driver strength described in the previous section (pll enabled, two port mode) have identical functionality with the pll disabled. as described earlier in the pll-enabled mode section, t od can vary depending on clkin frequency and interpolation rate. however, with the pll disabled, the input data latches are closely synchronized to dataclk so that it is recommended in this mode that the input data be timed from dataclk, not clkin. clkin dataclk data at ports 1 and 2 t od t h t s t s = 5.0ns t h = ?.2ns ( typ specs) figure 21. timing requirements in two port input mode with pll disabled pll disabled, one port mode in one port mode, data is received into the ad9775 as an inter- leaved stream on port 1. a clock signal (oneport clk), running at the interleaved data rate which is 2 the input data rate of the internal i and q channels is available for data syn- chronization at pin 32. with pll disabled, a clock at the dac output rate must be applied to clkin. internal dividers synthesize the oneportclk signal at pin 32. the selection of the data for the i or q channel is determined by the state of the logic level applied to pin 31 (iqsel when the ad9775 is in one port mode) on the rising edge of oneportclk. iqsel = 1 under these conditions will latch the data into the i channel on the clock rising edge, while iqsel = 0 will latch the data into the q channel. it is possible to invert the i and q selection by setting control register 02h, bit 1 to the invert state (logic ??. figure 22 illustrates the timing requirements for the data inputs as well as the iqsel input. note that the 1 interpolation rate is not available in the one port mode. one port mode is very useful when interfacing with devices such as analog devices?ad6622 or ad6623 transmit signal processors, in which two digital data channels have been inter- leaved (multiplexed).
rev. 0 ad9775 C25C the programmable modes?oneportclk inversion, oneportclk driver strength, and iq pairing described in the previous section (pll enabled, one port mode) have iden tical functionality with the pll disabled. t od t h t s clkin i and q interleaved input data at port 1 oneportclk iqsel t iqh t iqs t od = 4.7ns t s = 3.0ns t h = ?.0ns t iqs = 3.5ns t iqh = ?.5ns ( typ specs) figure 22. timing requirements in one port input mode with pll disabled digital filter modes the i and q data paths of the ad9775 have their own indepen- dent half-band fir filters. each data path consists of three fir filters, providing up to 8 interpolation for each channel. the rate of interpolation is determined by the state of control register 01h, bits 7 and 6. figures 1a?c show the response of the digi- tal filters when the ad9775 is set to 2 , 4 , and 8 modes. the frequency axes of these graphs have been normalized to the input data rate of the dac. as the graphs show, the digital filters can provide greater than 75 db of out-of-band rejection. an online tool is available for quick and easy analysis of the ad9775 interpolation filters in the various modes. the link can be accessed at: www.analog.com/techsupport/designtools/ interactivetools/dac/ad9777image.html. amplitude modulation given two sine waves at the same frequency, but with a 90 phase difference, a point of view in time can be taken such that the waveform that leads in phase is cosinusoidal and the waveform that lags is sinusoidal. analysis of complex variables states that the cosine waveform can be defined as having real positive and negative frequency components, while the sine waveform con sists of imaginary positive and negative frequency images. this is shown graphically in the frequency domain in figure 23. dc dc e ? t /2j cosine sine e ? t /2 e ? t /2j e ? t /2 figure 23. real and imaginary components of sinusoidal and cosinusoidal waveforms amplitude modulating a baseband signal with a sine or a cosine convolves the baseband signal with the modulating carrier in the frequency domain. amplitude scaling of the modulated signal reduces the positive and negative frequency images by a factor of two. this scaling will be very important in the discussion of the various modulation modes. the phase relationship of the modu- lated signals is dependent on whether the modulating carrier is sinusoidal or cosinusoidal, again with respect to the reference point of the viewer. examples of sine and cosine modulation are given in figure 24. s inusoidal m odulation dc dc ae ? t /2j ae ? t /2 ae ? t /2 ae ? t /2j cosinusoidal m odulation figure 24. baseband signal, amplitude modulated with sine and cosine carriers
rev. 0 ad9775 C26C modulation, no interpolation with control register 01h, bits 7 and 6 set to ?0,?the inter- polation function on the ad9775 is disabled. figures 25a?5d show the dac output spectral characteristics of the ad9775 in the vari ous modulation modes, all with the interpolation filters disabled. the m odulation frequency is determined by the state of control register 01h, bits 5 and 4. the tall rectangles represent the digital domain spectrum of a baseband signal of narrow bandwidth. by comparing the digital domain spectrum to the dac sin(x)/x roll-off, an estimate can be made for the characteristics required for the dac reconstruction filter. note also, per the previous discussion on amplitude modulation, that the spectral components (where modulation is set to f s /4 or f s /8) are scaled by a factor of 2. in the situation where the modula- tion is f s /2, the modulated spectral components add constructively and there is no scaling effect. f out ( f data ) 0 0.2 amplitude ?dbfs ?00 0 ?0 ?0 ?0 ?0 0.4 0.6 0.8 1.0 figure 25a. no interpolation, modulation disabled f out ( f data ) 0 0.2 amplitude ?dbfs ?00 0 ?0 ?0 ?0 ?0 0.4 0.6 0.8 1.0 figure 25b. no interpolation, modulation = f dac /2 f out ( f data ) 0 0.2 amplitude ?dbfs ?00 0 ?0 ?0 ?0 ?0 0.4 0.6 0.8 1.0 figure 25c. no interpolation, modulation = f dac /4 f out ( f data ) 0 0.2 amplitude ?dbfs ?00 0 ?0 ?0 ?0 ?0 0.4 0.6 0.8 1.0 figure 25d. no interpolation, modulation = f dac /8 figure 25. effects of digital modulation on dac output spectrum, interpolation disabled
rev. 0 ad9775 C27C modulation, interpolation = 2 with control register 01h, bits 7 and 6 set to ?1,?the inter- po lation rate of the ad9775 is 2 . modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (1, ?). figures 26a?6d represent the spectral re sponse of the ad9775 dac output with 2 interpolation in the various modulation modes to a narrow band baseband signal (again, the tall rectangles in the graphic). the advantage of interpolation becomes clear in figures 26a?6d, where it can be seen that the images that would normally appear in the spec- trum around the input data rate frequency are suppressed by >70 db. another significant point is that the interpolation filter- ing is done previous to the digital modulator. for this reason, as figures 26a?6d show, the pass band of the interpolation filters can be frequency shifted, giving the equivalent of a high pass digital filter. note that when using the f s /4 modulation mode, there is no true stop band as the band edges coincide with each other. in the f s /8 modulation mode, amplitude scaling occurs over only a portion of the digital filter pass band due to constructive addition over just that section of the band. figure 26. effects of digital modulation on dac output spectrum, interpolation = 2 f out ( f data ) 0 0.5 amplitude ?dbfs ?00 0 ?0 ?0 ?0 ?0 1.0 1.5 2.0 figure 26a. 2 interpolation, modulation = disabled f out ( f data ) 0 0.5 amplitude ?dbfs ?00 0 ?0 ?0 ?0 ?0 1.0 1.5 2.0 figure 26b. 2 interpolation, modulation = f dac /2 f out ( f data ) 0 0.5 amplitude ?dbfs ?00 0 ?0 ?0 ?0 ?0 1.0 1.5 2.0 figure 26c. 2 interpolation, modulation = f dac /4 f out ( f data ) 0 0.5 amplitude ?dbfs ?00 0 ?0 ?0 ?0 ?0 1.0 1.5 2.0 figure 26d. 2 interpolation, modulation = f dac /8
rev. 0 ad9775 C28C f out ( f data ) 01 amplitude ?dbfs ?00 0 ?0 ?0 ?0 ?0 234 figure 27a. 4 interpolation, modulation disabled f out ( f data ) 01 amplitude ?dbfs ?00 0 ?0 ?0 ?0 ?0 234 figure 27b. 4 interpolation, modulation = f dac /2 f out ( f data ) 01 amplitude ?dbfs ?00 0 ?0 ?0 ?0 ?0 234 figure 27c. 4 interpolation, modulation = f dac /4 f out ( f data ) 01 amplitude ?dbfs ?00 0 ?0 ?0 ?0 ?0 234 figure 27d. 4 interpolation, modulation = f dac /8 figure 27. effect of digital modulation on dac output spectrum, interpolation = 4 modulation, interpolation = 4 with control register 01h, bits 7 and 6 set to ?0,?the inter- po lation rate of the ad9775 is 4 . modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, 1, 0, ?). figures 27a?7d represent the spectral response of the ad9775 dac output with 4 interpo- lation in the various modulation modes to a narrow band baseband signal.
rev. 0 ad9775 C29C f out ( f data ) 01 amplitude ?dbfs ?00 0 ?0 ?0 ?0 ?0 234 figure 28a. 8 interpolation, modulation disabled f out ( f data ) 01 amplitude ?dbfs ?00 0 ?0 ?0 ?0 ?0 234 figure 28b. 8 interpolation, modulation = f dac /2 f out ( f data ) 01 amplitude ?dbfs ?00 0 ?0 ?0 ?0 ?0 234 5 678 figure 28c. 8 interpolation, modulation = f dac /4 f out ( f data ) 01 amplitude ?dbfs ?00 0 ?0 ?0 ?0 ?0 234 5 678 figure 28d. 8 interpolation, modulation = f dac /8 figure 28. effect of digital modulation on dac output spectrum, interpolation = 8 modulation, interpolation = 8 with control register 01h, bits 7 and 6 set to ?1,?the interpolation rate of the ad9775 is 8 . modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, 0.707, 1, 0.707, 0, ?.707, ?, 0.707). figures 28a?8d represent the spectral response of the ad9775 dac output with 8 interpolation in the various modulation modes to a narrow band baseband signal. looking at figures 26?9, the user can see how higher interpola- tion rates reduce the complexity of the reconstruction filter needed at the dac output. it also becomes apparent that the ability to modulate by f s /2, f s /4, or f s /8 adds a degree of flexibility in frequency planning. zero stuffing (control register 01h, bit 3) as shown in figure 29, a ??or null in the output frequency response of the dac (after interpolation, modulation, and dac reconstruction) occurs at the final dac sample rate (f dac ). this is due to the inherent sin(x)/x roll-off response in the digi tal- to-analog conversion. in applications where the desired fre quency content is below f dac /2, this may not be a problem. note that at f dac /2 the loss due to sin(x)/x is 4 db. in direct rf applica- tions, this roll-off may be problematic due to the increased pass band amplitude variation as well as the reduced amplitude of the desired signal. consider an application where the digital data into the ad9775 represents a baseband signal around f dac /4 with a pass band of f dac /10. the reconstructed signal out of the ad9775 would experience only a 0.75 db amplitude variation over its pass band. however, the image of the same signal occurring at 3 f dac /4 will suffer from a pass-band flatness variation of 3.93 db. this image may be the desired signal in an if application using one of the various modulation modes in the ad9775. this roll-off of image frequencies can be seen in figures 25 through 28, where the effect of the interpolation and modulation rate is apparent as well.
rev. 0 ad9775 C30C f out , normalized to f data with zero stuffing disabled ?hz sin (x)/x roll-off ?dbfs 0 0 ?0 ?0 ?0 ?0 ?0 0.5 10 1.0 1.5 2.0 zero stuffing enabled zero stuffing disabled figure 29. effect of zero stuffing on dacs sin(x)/ x response to improve upon the pass-band flatness of the desired image, the zero stuffing mode can be enabled by setting the control register bit to a logic ?.?this option increases the ratio of f dac /f data by a factor of 2 by doubling the dac sample rate and inserting a midscale sample (i.e., 1000 0000 0000 0000) after every data sample originating from the interpolation filter. this is important as it will affect the pll divider ratio needed to keep the vco within its optimum speed range. note that the zero stuffing takes place in the digital signal chain at the output of the digital modulator before the dac. the net effect is to increase the dac output sample rate by a factor of 2 with the ??in the sin(x)/x dac transfer function occurring at twice the original frequency. a 6 db loss in ampli- tude at low frequencies is also evident, as can be seen in figure 29. it is important to realize that the zero stuffing option by itself does not change the location of the images but rather their am pli- tude, pass-band flatness, and relative weighting. for instance, in the previous example, the pass-band amplitude flatness of the image at 3 f data /4 is now improved to 0.59 db while the signal level has increased slightly from ?0.5 dbfs to ?.1 dbfs. interpolating (complex mix mode) (control register 01h, bit 2) in the complex mix mode, the two digital modulators on the ad9775 are coupled to provide a complex modulation function. in conjunction with an external quadrature modulator, this complex modulation can be used to realize a transmit image rejection architecture. the complex modulation function can be programmed for e +j t or e ? t to give upper or lower image rejec- tion. as in the real modulation mode, the modulation frequency can be programmed via the spi port for f dac /2, f dac /4, and f dac /8, where f dac represents the dac output rate. operations on complex signals truly complex signals cannot be realized outside of a computer simulation. however, two data channels, both consisting of real data, can be defined as the real and imaginary components of a complex signal. i (real) and q (imaginary) data paths are often defined this way. by using the architecture defined in figure 30, a system can be realized that operates on complex signals, giving a complex (real and imaginary) output. if a complex modulation function (e +j t ) is desired, the real and imaginary components of the system correspond to the real and imaginary components of e +j t , or cos t and sin t. as figure 31 shows, the complex modulation function can be realized by applying these components to the structure of the com- plex system defined in figure 30. complex modulation and image rejection of baseband signals in traditional transmit applications, a two-step upconversion is done in which a baseband signal is modulated by one carrier to an if (intermediate frequency) and then modulated a second time to the transmit frequency. although this approach has several benefits, a major drawback is that two images are cre- ated near the transmit frequency. only one image is needed, the other being an exact duplicate. unless the unwanted image is filtered, typically with analog components, transmit power is wasted and the usable bandwidth available in the system is reduced. a more efficient method of suppressing the unwanted image can be achieved by using a complex modulator followed by a quadra ture modulator. figure 32 is a block diagram of a quadrature modulator. note that it is in fact the real output half of a com plex modulator. the complete upconversion can actu- ally be referred to as two complex upconversion stages, the real output of which becomes the transmitted signal. a(t) input input output output complex filter = (c + jd) imaginary b(t) b(t) a(t) + c b(t) c(t) b(t) + d b(t) figure 30. realization of a complex system output (imaginary) output (real) input (real) input (imaginary) e ? t = cos t + jsin t 90 figure 31. implementation of a complex modulator 90 output input (real) input (imaginary) cos t sin t figure 32. quadrature modulator
rev. 0 ad9775 C31C the entire upconversion, from baseband to transmit frequency, is represented graphically in figure 33. the resulting spectrum shown in figure 33 represents the complex data consisting of the baseband real and imaginary channels, now modulated onto orthogonal (cosine and negative sine) carriers at the transmit frequency. it is important to remember that in this application (two baseband data channels) the image rejection is not dependent on the data at either of the ad9775 input channels. in fact, image rejection will still occur with either one or both of the ad9775 input channels active. note that by changing the sign of the sinusoidal multiplying term in the complex modulator, the upper sideband image could have been suppressed while passing the lower one. this is easily done in the ad9775 by selecting the e +j t bit (register 01h, bit 1). in purely complex terms, figure 31 represents the two-stage upconversion from complex baseband to carrier. real channel (in) imaginary channel (in) dc dc a b complex modulator real channel (out) imaginary channel (out) ? c * b/2j ?/2j to quadrature modulator ? c ? c ? c f c f c ? c f c a/2j ?/2j b/2 b/2 a/2 a/2 real imaginary quadrature modulator out a /4 + b/4j a /4 ?b/4j ? q ?f c rejected images a /4 + b/4j a/4 ?b/4j a /4 + b/4j a/4 b/4j ?/4 ?b/4j ?/4 + b/4j a/2 + b/ 2j a/2 ?b/2j ? q * ? q + f c f q ?f c f q f q + f c ? q f q ? q f q * f c = complex modulation frequency * f q = quadrature modulation frequency figure 33. two-stage upconversion and resulting image rejection
rev. 0 ad9775 C32C output = real complex baseband signal dc = real e j( 1 + 2)t frequency 1 ? 2 1 + 2 1 1/2 1/2 figure 34. two-stage complex upconversion image rejection and sideband suppression of modulated carriers as shown in figure 33, image rejection can be achieved by applying baseband data to the ad9775 and following the ad9775 with a quadrature modulator. to process multiple carriers while still maintaining image reject capability, each carrier must be complex modulated. as figure 34 shows, single- or multiple-complex modulators can be used to synthesize complex carriers. these complex carriers are then summed and applied to the real and imaginary inputs of the ad9775. a system in which multiple baseband signals are complex modulated and then applied to the ad9775 real and imaginary inputs followed by a quadrature modulator is shown in figure 36, which also describes the transfer function of this system and the spectral output. note the simi- larity of the transfer functions given in figure 36 and figure 34. figure 36 adds an additional complex modulator stage for the purpose of summing multiple carriers at the ad9775 inputs. also, as in figure 33, the image rejection is not dependent on the real or imaginary baseband data on any channel. image rejection on a channel will occur if either the real or imaginary data, or both, is present on the baseband channel. it is important to remember that the magnitude of a complex signal can be 1.414 the magnitude of its real or imaginary components. due to this 3 db increase in signal amplitude, the real and imagi- nary inp uts to the ad9775 must be kept at least 3 db below full scale when operating with the complex modulator. overranging in the complex modulator will result in severe distortion at the dac output. r(1) ba seband channel 1 real input imaginary input r(1) complex modulator 1 ba seband channel n real input imaginary input complex modulator n r(n) r(n) ba seband channel 2 real input imaginary input r(2) r(2) complex modulator 2 r(n) = real output of n i(n) = imaginary output of n multicarrier real output = r(1) + r(2) + ...r(n) (t o real input of ad9775) multicarrier imaginary output = i(1) + i(2) + ...i(n) (t o imaginary input of ad9775) figure 35. synthesis of multicarrier complex signal real imaginary multiple complex modulators frequency = 1 , 2 ... n real imaginary real imaginary ad9775 complex modulator frequency = c quadrature modulator frequency = q multiple baseband channels real rejected images dc 1 ? c ? q 1 + c + q output = real e j( n + c + q )t complex baseband signal figure 36. image rejection with multicarrier signals
rev. 0 ad9775 C33C the complex carrier synthesized in the ad9775 digital modulator is accomplished by creating two real digital carriers in quadrature. carriers in quadrature cannot be created with the modulator running at f dac /2. as a result, complex modulation only functions with modulation rates of f dac /4 and f dac /8. regions a and b of figures 37 through 42 are the result of the complex signal described above, when complex modulated in the ad9775 by +e j t . regions c and d are the result of the complex signal described above, again with positive frequency components only, modulated in the ad9775 by ? j t . the analog quadra- tu re modulator after the ad9775 inherently modulates by +e j t . region a region a is a direct result of the upconversion of the complex signal near baseband. if viewed as a complex signal, only the images in region a will remain. the complex signal a, consisting of positive frequency components only in the digital domain, has images in the positive odd nyquist zones (1, 3, 5...) as well as images in the negative even nyquist zones. the appearance and rejection of images in every other nyquist zone will become more apparent at the output of the quadrature modulator. the a images will appear on the real and the imaginary outputs of the ad9775, as well as on the output of the quadrature modula- tor, where the center of the spectral plot will now represent the quadrature modulator lo, and the horizontal scale now repre- sents the frequency offset from this lo. region b region b is the image (complex conjugate) of region a. if a spec- trum analyzer is used to view the real or imaginary dac outputs of the ad9775, region b will appear in the spectrum. however, on the output of the quadrature modulator, region b will be rejected. region c region c is most accurately described as a down conversion, as the modulating carrier is ? j t . if viewed as a complex signal, only the images in region c will remain. this image will appear on the real and imaginary outputs of the ad9775, as well as on the output of the quadrature modulator, where the center of the spec- tral plot will now represent the quadrature modulator lo and the horizontal scale will represent the frequency offset from this lo. region d region d is the image (complex conjugate) of region c. if a spectrum analyzer is used to view the real or imaginary dac outputs of the ad9775, region d will appear in the spectrum. however, on the output of the quadrature modulator, region d will be rejected. figures 43 through 50 show the measured response of the ad9775 and ad8345 given the complex input signal to the ad9775 in figure 43. the data in these graphs was taken with a data rate of 12.5 msps at the ad9775 inputs. the interpolation rate of 4 or 8 gives a dac output data rate of 50 msps or 100 msps. as a result, the high end of the dac output spectrum in these graphs is the first null point for the sin(x)/x roll-off, and the asymmetry of the dac output images is representative of the sin(x)/x roll-off over the spectrum. the internal pll was enabled for these results. in addition, a 35 mhz third order low-pass filter was used at the ad9775/ad8345 interface to suppress dac images. an important point can be made by looking at figures 45 and 47. figure 45 represents a group of positive frequencies modulated by complex +f dac /4, while figure 47 represents a group of negative frequencies modulated by complex ? dac /4. when looking at the real or imaginary outputs of the ad9775, as shown in figures 45 and 47, the results look identical. however, the spectrum analyzer cannot show the phase relationship of these signals. the differ- ence in phase between the two signals becomes apparent when they are applied to the ad8345 quadrature modulator, with the results shown in figures 46 and 48.
rev. 0 ad9775 C34C dabcdabc f out ( f data ) ?.0 ?00 ?0 ?0 ?0 ?0 0 ?.5 ?.0 ?.5 0 0.5 1.0 1.5 2.0 (lo) figure 37. 2 interpolation, complex f dac /4 modulation dabc da bc f out ( f data ) ?.0 ?00 ?0 ?0 ?0 ?0 0 ?.0 ?.0 ?.0 0 1.0 2.0 3.0 4.0 (lo) figure 38. 4 interpolation, complex f dac /4 modulation da bc da bc f out ( f data ) ?.0 ?00 ?0 ?0 ?0 ?0 0 ?.0 ?.0 ?.0 0 2.0 4.0 6.0 8.0 (lo) figure 39. 8 interpolation, complex f dac /4 modulation abcdab f out ( f data ) ?.0 ?00 ?0 ?0 ?0 ?0 0 ?.5 ?.0 ?.5 0 0.5 1.0 1.5 2.0 (lo) c d figure 40. 2 interpolation, complex f dac /8 modulation abcda b f out ( f data ) ?.0 ?00 ?0 ?0 ?0 ?0 0 ?.0 ?.0 ?.0 0 1.0 2.0 3.0 4.0 (lo) c d figure 41. 4 interpolation, complex f dac /8 modulation f out ( f data ) ?.0 ?00 ?0 ?0 ?0 ?0 0 ?.0 ?.0 ?.0 0 2.0 4.0 6.0 8.0 (lo) a d c b a d c b figure 42. 8 interpolation, complex f dac /8 modulation
rev. 0 ad9775 C35C amplitude ?dbm ?0 ?00 010 50 20 ?0 ?0 ?0 ?0 ?0 ?0 ?0 frequency ?mhz ?0 0 30 40 figure 43. ad9775, real dac output of complex input signal near baseband (positive frequencies only), interpolation = 4 , no modulation in ad9775 amplitude ?dbm ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 750 frequency ?mhz 760 770 780 790 800 810 820 830 840 850 figure 44. ad9775 complex output from figure 43, now quadrature modulated by ad8345 (lo = 800 mhz) amplitude ?dbm ?0 ?00 02040 ?0 ?0 ?0 ?0 ?0 ?0 ?0 frequency ?mhz ?0 0 30 50 10 figure 45. ad9775, real dac output of complex input signal near baseband (positive frequencies only), interpolation = 4 , complex modulation in ad9775 = +f dac /4 amplitude ?dbm ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 750 frequency ?mhz 760 770 780 790 800 810 820 830 840 850 figure 46. ad9775 complex output from figure 45, now quadrature modulated by ad8345 (lo = 800 mhz) * windows is a registered trademark of microsoft corporation
rev. 0 ad9775 C36C amplitude ?dbm ?0 ?00 02040 ?0 ?0 ?0 ?0 ?0 ?0 ?0 frequency ?mhz ?0 0 30 50 10 figure 47. ad9775, real dac output of complex input signal near baseband (negative frequen cies only), interpolation = 4 , complex modulation in ad9775 = Cf dac /4 amplitude ?dbm ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 750 frequency ?mhz 760 770 780 790 800 810 820 830 840 850 figure 48. ad9775 complex output from figure 47, now quadrature modulated by ad8345 (lo = 800 mhz) amplitude ?dbm ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 020 80 40 frequency ?mhz 60 100 figure 49. ad9775, real dac output of complex input signal near baseband (positive frequencies only), interpolation = 8 , complex modulation in ad9775 = +f dac /8 amplitude ?dbm ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 700 frequency ?mhz 720 740 760 780 800 820 840 860 880 900 figure 50. ad9775 complex output from figure 49, now quadrature modulated by ad8345 (lo = 800 mhz)
rev. 0 ad9775 C37C applying the ad9775 output configurations the following sections illustrate typical output configurations for the ad9775. unless otherwise noted, it is assumed that i outfs is set to a nominal 20 ma. for applications requiring optimum dynamic performance, a differential output configuration is suggested. a simple differential output may be achieved by con- verting i outa and i outb to a voltage output by terminating them to agnd via equal value resistors. this type of configura- tion may be useful when driving a differential voltage input device such as a modulator. if a conversion to a single-ended signal is desired and the application allows for ac-cou pling, an rf t ransformer may be useful, or if power gain is required, an op amp may be used. the transformer configuration provides optimum high frequency noise and distortion performance. the differen- tial op amp configuration is suitable for applications requiring dc-coupling, signal gain, and/or level shifting within the band- width of the chosen op amp. a single-ended output is suitable for applications requiring a unipolar voltage output. a positive unipolar output voltage will result if i outa and/or i outb is connected to a load resistor, r load , referred to agnd. this configuration is most suitable f or a single-supply system requiring a dc-coupled, ground re ferred output voltage. alternatively, an amplifier could be configured as an i-v converter, thus converting i outa or i outb into a nega- tive unipolar voltage. this configuration provides the best dac dc linearity as i outa or i outb are maintained at ground or vir- tual ground. unbuffered differential output, equivalent circuit in many applications, it may be necessary to understand the equivalent dac output circuit. this is especially useful when designing output filters or when driving inputs with finite input impedances. figure 51 illustrates the output of the ad9775 and the equivalent circuit. a typical application where this information may be useful is when designing an interface filter between the ad9775 and analog devices?ad8345 quadrature m odulator. i outa r a + r b i outb v out (differential) v source = i outfs (r a + r b ) p-p v out + v out figure 51. dac output equivalent circuit for the typical situation, where i outfs = 20 ma and r a and r b both equal 50 ? , the equivalent circuit values become: v source = 2 v p-p r out = 100 ? note that the output impedance of the ad9775 dac itself is greater than 100 k ? and typically has no effect on the imped ance of the equivalent output circuit. differential coupling using a transformer an rf transformer can be used to perform a differential- to-single-ended signal conversion as shown in figure 52. a differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer? pass band. an rf transformer such as the mini-circuits t1-1t provides excellent rejection of common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. it also provides electrical isolation and the ability to deliver twice the power to the load. trans- formers with different impedance ratios may also be used for impedance matching purposes. i outa i outb dac r load mini-circuits t1-t2 figure 52. transformer-coupled output circuit the center tap on the primary side of the transformer must be connected to agnd to provide the necessary dc current path for both i outa and i outb . the complementary voltages appearing at i outa and i outb (i.e., v outa and v outb ) swing symm etrically around agnd and should be maintained within the specified output compliance range of the ad9775. a differential resistor, r diff , may be inserted in applications where the output of the transformer is connected to the load, r load , via a passive recon- struction filter or cable. r diff is determined by the transformer? impedance ratio and provides the proper source termination that results in a low vswr. note that approximately half the signal power will be dissipated across r diff . differential coupling using an op amp an op amp can also be used to perform a differential-to-single- ended conversion as shown in figure 53. this has the added benefit of providing signal gain as well. in figure 53, the ad9775 is configured with two equal load resistors, r load , of 25 ? . the differential voltage developed across i outa and i outb is converted to a single-ended signal via the differential op amp configura- tion. an optional capacitor can be installed across i outa and i outb , forming a real pole in a low pass filter. the addition of this capacitor also enhances the op amp? distortion performance by preventing the dac? fast slewing output from overloading the input of the op amp. i outa i outb dac 25 ad8021 500 c opt 225 225 500 r opt 225 avdd 25 figure 53. op amp-coupled output circuit the common-mode (and second order distortion) rejection of this configuration is typically determined by the resistor matching. the op amp used must operate from a dual supply since its output is approximately 1.0 v. a high speed amplifier, such as the ad8021, capable of preserving the differential per formance
rev. 0 ad9775 C38C of the ad9775 while meeting other system level objectives (i.e., cost, power) is recommended. the op amp? differential gain, its gain setting resistor values, and full-scale output swing capa- bilities should all be considered when optimizing this cir cuit. r opt is only necessary if level shifting is required on the op amp out- put. in figure 53, avdd, which is the positive analog sup ply for both the ad9775 and the op amp, is also used to level shift the differential output of the ad9775 to midsupply (i.e., avdd/2). interfacing the ad9775 with the ad8345 quadrature modulator the ad9775 architecture was defined to operate in a transmit signal chain using an image reject architecture. a quadrature modulator is also required in this application and should be designed to meet the output characteristics of the dac as much as possible. the ad8345 from analog devices meets many of the requirements for interfacing with the ad9775. as with any dac output interface, there are a number of issues that have to be resolved. among the major issues are the following. dac compliance voltage/input common-mode range the dynamic range of the ad9775 is optimal when the dac outputs swing between 1.0 v. the input common-mode range of the ad8345, at 0.7 v, allows optimum dynamic range to be achieved in both components. gain/offset adjust the matching of the dac output to the common-mode input of the ad8345 allows the two components to be dc-coupled, with no level shifting necessary. the combined voltage offset of the two parts can therefore be compensated for via the ad9775 programmable offset adjust. this allows excellent lo cancella- tion at the ad8345 output. the programmable gain adjust allows for optimal image rejection as well. the ad9775 evaluation board includes an ad8345 and recom- mended interface (figures 59 and 60). on the output of the ad9775, r9 and r10 convert the dac output current to a voltage. r16 may be used to do a slight common-mode shift if necessary. the (now voltage) signal is applied to a low pass reconstruction filter to reject dac images. the components installed on the ad9775 provide a 35 mhz cutoff, but may be changed to fit the application. a balun (mini-circuits adtl1-12) is used to cross the ground plane boundary to the ad8345. another balun (mini-circuits etc1-1-13) is used to couple the lo input of the ad8345. the interface requires a low ac impedance return path from the ad8345, so a single connec- tion between the ad9775 and ad8345 ground planes is recommended. the performance of the ad9775 and ad8345 in an image reject transmitter, reconstructing three wcdma carriers, can be seen in figure 54. the lo of the ad8345 in this application is 800 mhz . image rejection (50 db) and lo feedthrough (?8 dbfs) have been optimized with the programmable features of the ad9775. the average output power of the digital waveform for this test was set to ?5 dbfs to account for the peak-to-average ratio of the wcdma signal. frequency ?mhz amplitude ?dbm ?0 0 762.5 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 782.5 802.5 822.5 842.5 figure 54. ad9775/ad8345 synthesizing a three- carrier wcdma signal at an lo of 800 mhz evaluation board the ad9775 evaluation board allows easy configuration of the various modes, programmable via the spi port. software is available for programming the spi port from either win95 or win98 . the evaluation board also contains an ad 8345 quadra- ture modulator and support circuitry that allows the user to optimally configure the ad9775 in an image reject transmit signal chain. figures 55 through 58 describe how to configure the evaluation board in the one and two port input modes with the pll enabled and disabled. refer to figures 59 through 68, the schematics, and the layout for the ad9775 evaluation board for the jumper locations de scribed below. the ad9775 outputs can be configured for various applications by referring to the follow- ing instructions. dac single-ended outputs remove transformers t2 and t3. solder jumper links jp4 or jp28 to look at the dac1 outputs. solder jumper links jp29 or jp30 to look at the dac2 outputs. jumpers 8 and 13?7 should remain unsoldered. the jumpers jp35?p38 may be used to ground one of the dac outputs while the other is measured single-ended. optimum single-ended distortion performance is typically achieved in this manner. the outputs are taken from s3 and s4. dac differential outputs transformers t2 and t3 should be in place. note that the lower band of operation for these transformers is 300 khz to 500 khz. jumpers 4, 8, 13?7, and 28?0 should remain unsoldered. the outputs are taken from s3 and s4. using the ad8345 remove transformers t2 and t3. jumpers jp4 and 28?0 should remain unsoldered. jumpers 13?6 should be soldered. the desired components for the low pass interface filter l6, l7, c55, and c81 should be in place. the lo drive is connected to the ad8345 via j10 and the balun t4; and the ad8345 output is taken from j9. win95 and win98 are a registered trademarks of microsoft corporation.
rev. 0 ad9775 C39C s ignal generator clk+/clk dataclk lecroy pu lse gene rator t rig inp awg2021 or dg2020 input clock dac1, db11?b0 ad9775 dac2, db11?b0 40-pin ribbon cable ju mper configuration for two port mode pll on soldered/in unsoldered/out jp1 ? jp2 jp3 ? jp5 ? jp6 ? jp12 ? jp24 ? jp25 ? jp26 ? jp27 ? jp31 ? jp32 ? jp33 ? figure 55. test configuration for ad9775 in two port mode with pll enabled, signal generator frequency = input data rate, dac output data rate = signal generator frequency interpolation rate s ignal generator clk+/clk oneportclk lecroy pu lse gene rator t rig inp awg2021 or dg2020 input clock dac1, db11?b0 ad9775 dac2, db11?b0 ju mper configuration for two port mode pll on soldered/in unsoldered/out jp1 ? jp2 ? jp3 ? jp5 ? jp6 ? jp12 ? jp24 ? jp25 ? jp26 ? jp27 ? jp31 ? jp32 ? jp33 ? figure 56. test configuration for ad9775 in one port mode with pll enabled, signal generator frequency = one-half interleaved input data rate, oneportclk = interleaved input data rate, dac output data rate = signal generator frequency interpolation rate
rev. 0 ad9775 C40C s ignal generator clk+/clk dataclk lecroy pu lse gene rator t rig inp awg2021 or dg2020 input clock dac1, db11?b0 ad9775 dac2, db11?b0 40-pin ribbon cable ju mper configuration for two port mode pll off soldered/in unsoldered/out jp1 ? jp2 ? jp3 ? jp5 ? jp6 ? jp12 ? jp24 ? jp25 ? jp26 ? jp27 ? jp31 ? jp32 ? jp33 ? figure 57. test configuration for ad9775 in two port mode with pll disabled, dac output data rate = signal generator frequency, dataclk = signal generator frequency/interpolation rate s ignal generator clk+/clk oneportclk lecroy pu lse gene rator t rig inp awg2021 or dg2020 input clock dac1, db11?b0 ad9775 dac2, db11?b0 ju mper configuration for two port mode pll off soldered/in unsoldered/out jp1 ? jp2 ? jp3 ? jp5 ? jp6 ? jp12 ? jp24 ? jp25 ? jp26 ? jp27 ? jp31 ? jp32 ? jp33 ? figure 58. test configuration for ad9775 in one port mode with pll disabled, dac output data rate = signal generator frequency, oneportclk = interleaved input data rate = 2 signal generator frequency/interpolation rate
rev. 0 ad9775 C41C jp18 vddmin vddm j10 dgnd; 3, 4, 5 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ibbp s p t6 adtl1-12 sp 1 34 6 4 61 3 c78 0.1 f c75 0.1 f c35 10 f c72 10 f 10v p s c78 0.1 f 1 3 4 5 c77 100pf t5 adtl1-12 t4 etc1-1-13 r30 dnp r28 0 local osc input r26 1k j7 j21 c74 100pf j10 dgnd; 3, 4, 5 modulated output r23 0 r33 51 r34 dnp c79 dnp j19 r32 51 c81 dnp c55 dnp o2p l7 dnp l6 dnp r36 51 r37 dnp c80 dnp j20 r35 51 c73 dnp c54 dnp o1p l5 dnp l4 dnp o1n o2n dvdd_in j8 agnd c65 22 f 16v j5 c67 0.1 f c66 22 f 16v j9 l3 ferrite tp2 red dvdd tp3 blk avdd_in j4 agnd c64 22 f 16v j6 c68 0.1 f c61 22 f 16v j10 l2 ferrite tp4 red avdd tp5 blk clkvdd_in j3 agnd c63 22 f 16v j7 c69 0.1 f c62 22 f 16v j11 l1 ferrite tp6 red clkvdd tp7 blk vddmin w11 c28 22 f 16v w12 c32 0.1 f l8 ferrite vddm power input filters figure 59. ad8345 circuitry on ad9775 evaluation board
rev. 0 ad9775 C42C tp14 wht bd08 bd09 bd10 bd11 bd12 bd13 ad00 ad01 ad03 ad04 ad05 ad07 ad08 ad09 ad10 ad11 ad12 ad13 ad14 ad15 ad06 ad02 o1n o1p o2n o2p u1 ad9775 clkn clkp dclk-plll fsadj1 fsadj2 iout1n iout1p iout2n iout2p p1d0 p1d1 p1d10 p1d11 p1d12 p1d13 p1d14 p1d15 p1d2 p1d3 p1d4 p1d5 p1d6 p1d7 p1d8 p1d9 p2d0 p2d1 p2d10 p2d11 p2d12 p2d13 p2d14-opclk p2d15-iqsel p2d2 p2d3 p2d4 p2d5 p2d6 p2d7 p2d8 p2d9 refout reset sp-clk sp-csb sp-sdo sp-sdi vdda1 vdda2 vdda3 vdda4 vdda5 vdda6 vddc1 vddc2 vddd1 vssd2 vddd3 vddd4 vddd5 vddd6 vssa1 vssa10 vssa2 vssa3 vssa4 vssa5 vssa6 vssa7 vssa8 vssa9 vssc1 vssc2 vssd1 vddd2 vssd3 vssd4 vssd5 vssd6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 lf c59, dnp c57, dnp spsdo spsdi spclk spcsp bd03 bd02 bd01 bd00 bd04 bd05 bd06 bd07 r6 1k c21 0.001 f c5 10 f 6.3v dvdd c22 0.001 f c6 10 f 6.3v dvdd tp11 wht tp10 wht tp9 wht tp8 wht c16 0.1 f c4 10 f 6.3v r7 2k c18 0.1 f r8 2k c17 0.1 f c15 0.1 f c3 10 f 6.3v c58, dnp avdd c58, dnp c20 0.1 f c19 0.1 f c14 0.1 f c2 10 f 6.3v avdd 3 2 1 4 5 6 j37 j35 j36 j38 j13 j15 j16 j14 j28 t2 t1-1t j4 r9, 51 r10, 51 j8 c70, 0.1 f r16, 10 r42 49.9 s3 3 2 1 4 5 6 j30 t3 t1-1t j29 r43 49.9 s4 out1 out2 r11, 51 r12, 51 j17 c70, 0.1 f r17, 10 agnd;3,4,5 agnd;3,4,5 c36 0.1 f c37 0.1 f c38 0.1 f c39 0.1 f c40 0.1 f c41 0.1 f dvdd c12 0.1 f c11 0.1 f c42 0.1 f c1 10 f 6.3v clkvdd c26 0.001 f c10 10 f 6.3v dvdd c25 0.001 f c9 10 f 6.3v dvdd c24 0.001 f c8 10 f 6.3v dvdd c23 0.001 f c7 10 f 6.3v dvdd 3 2 1 4 5 6 t1 t1-1t r1 200 j23 j22 r3 1k r2 1k c13 0.1 f r38, 10k j33 j24 j25 11 cx3 r5 49.9 dvdd; 14 agnd; 7 12 13 cx2 cx1 j12 dvdd r40 200 j1 adclk clkin r4 49.9 tp15 wht j2 j3 dataclk s2 c29 0.1 f j5 agnd;3,4,5 bd15 j40 opclk_3 j27 s6 agnd;3,4,5 iq s5 iq opclk agnd;3,4,5 c45 0.01 f j34 opclk 11 j31 j26 j32 bd14 r39 1k 12 13 74vcx86 74vcx86 s1 agnd;3,4,5 figure 60. ad9775 clock, power supplies, and output circuitry
rev. 0 ad9775 C43C rp1, 22 ad15 ad14 ad13 ad12 ad11 ad10 ad09 ad08 ad07 ad06 ad05 ad04 ad03 ad02 ad01 ad00 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 116 rp1, 22 215 ribbon r2 2 1 r3 3 r4 4 r5 5 r6 6 r7 7 r8 8 r9 9 10 r1 rcon r1 1 r2 2 r3 3 r4 4 r5 5 r6 6 r7 7 r8 8 9 r9 10 rcon rp5 50 rp1, 22 314 rp1, 22 413 rp1, 22 512 rp1, 22 611 rp1, 22 710 rp2, 22 89 rp2, 22 116 rp2, 22 215 rp2, 22 314 rp2, 22 413 rp2, 22 512 rp2, 22 611 rp2, 22 710 rp2, 22 89 r1 2 1 r1 3 r1 4 r1 5 r1 6 r1 7 r1 8 r1 9 10 r1 rcon r1 1 r2 2 r3 3 r4 4 r5 5 r6 6 r7 7 r8 8 9 r9 10 rcon data-a j1 adclk r15 220 rp6 50 rp7 dnp rp8 dnp 3 2 1 74vcx86 j clk k clr pre q_ q 3 1 2 opclk_3 dvdd opclk_2 dvdd; 14 agnd; 7 u4 74lcx112 u7 5 6 4 15 opclk 3 2 1 74vcx86 dvdd; 14 agnd; 7 u4 6 5 4 74vcx86 dvdd; 14 agnd; 7 u4 8 10 9 74vcx86 dvdd; 14 agnd; 7 u4 cx1 cx1 cx3 c33 0.1 f c30 4.7 f 6.3v dvdd 8 10 9 74vcx86 dvdd; 14 agnd; 7 u4 6 5 4 74vcx86 dvdd; 14 agnd; 7 u4 c34 0.1 f c31 4.7 f 6.3v dvdd j clk k clr pre q_ q 11 12 13 74lcx112 u7 9 7 10 14 agnd; 8 dvdd; 16 c53 0.1 f c52 4.7 f 6.3v dvdd figure 61. ad9775 evaluation board input (a channel) and clock buffer circuitry
rev. 0 ad9775 C44C c50 0.1 f c43 4.7 f 6.3v dvdd c51 0.1 f c44 4.7 f 6.3v dvdd agnd; 7 dvdd; 14 u5 74ac14 12 agnd; 7 dvdd; 14 u5 74ac14 12 13 agnd; 7 dvdd; 14 u5 74ac14 43 agnd; 7 dvdd; 14 u5 74ac14 10 11 agnd; 7 dvdd; 14 u5 74ac14 65 agnd; 7 dvdd; 14 u5 74ac14 89 1 2 3 4 5 6 p1 spi port spcsb spclk spsdi spsdo agnd; 7 dvdd; 14 u6 74ac14 1 2 agnd; 7 dvdd; 14 u6 74ac14 13 12 agnd; 7 dvdd; 14 u6 74ac14 3 4 agnd; 7 dvdd; 14 u6 74ac14 11 10 agnd; 7 dvdd; 14 u6 74ac14 5 6 agnd; 7 dvdd; 14 u6 74ac14 9 8 r50 9k r48 9k r45 9k rp3, 22 bd15 bd14 bd13 bd12 bd11 bd10 bd09 bd08 bd07 bd06 bd05 bd04 bd03 bd02 bd01 bd00 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 116 rp3, 22 215 ribbon r2 2 1 r3 3 r4 4 r5 5 r6 6 r7 7 r8 8 r9 9 10 r1 rcon r1 1 r2 2 r3 3 r4 4 r5 5 r6 6 r7 7 r8 8 9 r9 10 rcon rp12 50 rp3, 22 314 rp3, 22 413 rp3, 22 512 rp3, 22 611 rp3, 22 710 rp4, 22 89 rp4, 22 116 rp4, 22 215 rp4, 22 314 rp4, 22 413 rp4, 22 512 rp4, 22 611 rp4, 22 710 rp4, 22 89 r1 2 1 r1 3 r1 4 r1 5 r1 6 r1 7 r1 8 r1 9 10 r1 rcon r1 1 r2 2 r3 3 r4 4 r5 5 r6 6 r7 7 r8 8 9 r9 10 rcon data-b j2 rp11 50 rp9 dnp rp10 dnp figure 62. ad9775 evaluation board input (b channel) and spi port circuitry
rev. 0 ad9775 C45C figure 63. ad9775 evaluation board components, top side figure 64. ad9775 evaluation board components, bottom side
rev. 0 ad9775 C46C figure 65. ad9775 evaluation board layout, layer one (top) figure 66. ad9775 evaluation board layout, layer two (ground plane)
rev. 0 ad9775 C47C figure 67. ad9775 evaluation board layout, layer three (power plane) figure 68. ad9775 evaluation board layout, layer four (bottom)
rev. 0 C48C c02858C0C5/02(0) printed in u.s.a. ad9775 outline dimensions 80-lead, thermally enhanced, thin plastic quad flatpack [tqfp] (sv-80) dimensions shown in millimeters and (inches) 0.15 (0.0059) 0.05 (0.0020) 0.27 (0.0106) 0.22 (0.0087) 0.17 (0.0067) 0.20 (0.0079) 0.09 (0.0035) 0.50 (0.0197) bsc gage plane 0.25 (0.0098) 7 3.5 0 1.05 (0.0413) 1.00 (0.0394) 0.95 (0.0374) 1 20 21 41 40 60 80 61 pin 1 top view (pins down) 14.00 (0.5512) sq 12.00 (0.4724) sq seating plane 1.20 (0.0472) max 0.75 (0.0295) 0.60 (0.0236) 0.45 (0.0177) 1 20 21 41 40 60 80 61 6.00 (0.2362) sq bottom view coplanarity controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards mo-026-add an application note detailing the thermally enhanced tqfp can be found at; www.amkor.com/products/notes_papers/mlf_appnote_0301.pdf

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